External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

4.2. LPDDR3 Guidance

The LPDDR3 SDRAM Controller intellectual property (IP) enables you to implement LPDDR3 SDRAM interfaces with Arria® 10 and Stratix® 10 devices.

For all practical purposes, you can regard the TimeQuest timing analyzer's report on your memory interface as definitive for a given set of memory and board timing parameters. You can find timing information under Report DDR in TimeQuest and on the Timing Analysis tab in the parameter editor.

The following flowchart illustrates the recommended process to follow during the design phase, to determine timing margin and make iterative improvements to your design.



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