External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

4.2.2. LPDDR3 Layout Guidelines

The following table lists the LPDDR3 SDRAM general routing layout guidelines.

Table 42.  LPDDR3 Layout Guidelines



Max Length Discrete

500 ps.

Data Group Skew

Match DM and DQ within 5 ps of DQS.

Address/Command vs Clock Skew

Match Address/Command signals within 10 ps of mem CK.

Package Skew Matching


Clock matching

  • 2 ps within a clock pair
  • 5 ps between clock pairs
Spacing Guideline Data/Data Strobe/Address/Command 3H spacing between any Data and Address/Command traces, where H is distance to the nearest return path.
Spacing Guideline Mem Clock 5H spacing between mem clock and any other signal, where H is distance to the nearest return path.

Did you find the information on this page useful?

Characters remaining:

Feedback Message