External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

1.2. Guidelines for Intel® Arria® 10 External Memory Interface IP

The Intel® Arria® 10 device contains up to two I/O columns that can be used by external memory interfaces. The Arria® 10 I/O subsystem resides in the I/O columns. Each column contains multiple I/O banks, each of which consists of four I/O lanes. An I/O lane is a group of twelve I/O ports.

The I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for every physical I/O pin can be uniquely identified using the Bank Number and Index within I/O Bank values which are defined in each Arria 10 device pin-out file.

  • The numeric component of the Bank Number value identifies the I/O column, while the letter represents the I/O bank.
  • The Index within I/O Bank value falls within one of the following ranges: 0 to 11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4, respectively.
  • The adjacent I/O bank is defined as the I/O bank with same column number but the letter is either before or after the respective I/O bank letter in the A-Z system.
  • The pairing pin for an I/O pin is located in the same I/O bank. You can identify the pairing pin by adding one to its Index within I/O Bank number (if it is an even number), or by subtracting one from its Index within I/O Bank number (if it is an odd number).

For example, a physical pin with a Bank Number of 2K and Index within I/O Bank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2K, in column 2. The adjacent I/O banks are 2J and 2L. The pairing pin for this physical pin is the pin with an Index within I/O Bank of 23 and Bank Number of 2K.

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