1.2.1. General Pin-Out Guidelines for Arria® 10 EMIF IP
If you are using the Altera hard memory controller, you should employ the relative pin locations defined in the <variation_name>/altera_emif_arch_nf_version number/<synth|sim>/<variation_name>_altera_emif_arch_nf_version number_<unique ID>_readme.txt file, which is generated with your IP.
- EMIF IP pin-out requirements for the Arria® 10 Hard Processor Subsystem (HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IP defines a fixed pin-out in the Quartus Prime IP file (.qip), based on the IP configuration. When targeting Arria® 10 HPS, you do not need to make location assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the Quartus Prime software. Alternatively, consult the device handbook or the device pin-out files. For information on how you can customize the HPS EMIF pin-out, refer to Restrictions on I/O Bank Usage for Arria 10 EMIF IP with HPS.
- Ping Pong PHY, PHY only, RLDRAMx , QDRx and LPDDR3 are not supported with HPS.
Observe the following general guidelines for placing pins for your Arria 10 external memory interface:
- Ensure that the pins of a single external memory interface reside within a single I/O column.
- An external memory interface can occupy one or more banks in the same I/O column. When an interface must occupy multiple banks, ensure that those banks are adjacent to one another.
- Be aware that any pin in the same bank that is not used by an external memory interface is available for use as a general purpose I/O of compatible voltage and termination settings.
- All address and command pins and their associated clock pins (CK and CK#) must reside within a single bank. The bank containing the address and command pins is identified as the address and command bank.
- To minimize latency, when the interface uses more than two banks, you must select the center bank of the interface as the address and command bank.
- The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the Arria 10 External Memory Interface Pin Information File, which is available on www.altera.com.
You do not have to place every address and command pin manually. If you assign the location for one address and command pin, the Fitter automatically places the remaining address and command pins.Note: The pin-out scheme is a hardware requirement that you must follow, and can vary according to the topology of the memory device. Some schemes require three lanes to implement address and command pins, while others require four lanes. To determine which scheme to follow, refer to the messages window during parameterization of your IP, or to the <variation_name>/altera_emif_arch_nf_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nf_<version>_<unique ID>_readme.txt file after you have generated your IP.
- An unused I/O lane in the address and command bank can serve to implement a data group, such as a x8 DQS group. The data group must be from the same controller as the address and command signals.
- An I/O lane must not be used by both address and command pins and data pins.
- Place read data groups according to the DQS grouping in the pin table and pin planner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQ and CQ# / QK and QK#) must reside at physical pins capable of functioning as DQS/CQ and DQSn/CQn for a specific read data group size. You must place the associated read data pins (such as DQ and Q), within the same group.
- Unlike other device families, there is no need to swap CQ/CQ# pins in certain QDR II and QDR II+ latency configurations.
- QDR-IV requires that the polarity of all QKB/QKB# pins be swapped with respect to the polarity of the differential buffer inputs on the FPGA to ensure correct data capture on port B. All QKB pins on the memory device must be connected to the negative pins of the input buffers on the FPGA side, and all QKB# pins on the memory device must be connected to the positive pins of the input buffers on the FPGA side. Notice that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).
- You can use a single I/O lane to implement two x4 DQS groups. The pin table specifies which pins within an I/O lane can be used for the two pairs of DQS and DQS# signals. In addition, for x4 DQS groups you must observe the following rules:
- There must be an even number of x4 groups in an external memory interface.
- DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly, DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS group X and DQS group X+1 must be in the same I/O lane, where X is an even number.
- You should place the write data groups according to the DQS grouping in the pin table and pin planner. Output-only data clocks for QDR II, QDR II+, and QDR II+ Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, but must be placed on a differential pin pair. They must be placed in the same I/O bank as the corresponding DQS group.
For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.
- For protocols and topologies with bidirectional data pins where a write data group consists of multiple read data groups, you should place the data groups and their respective write and read clock in the same bank to improve I/O timing.
You do not need to specify the location of every data pin manually. If you assign the location for the read capture strobe/clock pin pairs, the Fitter will automatically place the remaining data pins.
- Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/O pin and another in the pairing pin for that I/O pin. It is recommended—though not required—that you follow the same rule for DBI pins, so that at a later date you have the freedom to repurpose the pin as DM.
- x4 mode does not support DM/DBI, or Arria 10 EMIF IP for HPS.
- If you are using an Arria 10 EMIF IP-based RLDRAM II or RLDRAM 3 external memory interface, you should ensure that all the pins in a DQS group (that is, DQ, DM, DK, and QK) are placed in the same I/O bank. This requirement facilitates timing closure and is necessary for successful compilation of your design.
Multiple Interfaces in the Same I/O Column
To place multiple interfaces in the same I/O column, you must ensure that the global reset signals (global_reset_n) for each individual interface all come from the same input pin or signal.
I/O Banks Selection
- For each memory interface, select consecutive I/O banks.
- A memory interface can only span across I/O banks in the same I/O column.
- Because I/O bank 2A is also employed for configuration-related operations, you can use it to construct external memory interfaces only when the following conditions are met:
- The pins required for configuration related use (such as configuration bus for Fast Passive Parallel mode or control signals for Partial Reconfiguration) are never shared with pins selected for EMIF use, even after configuration is complete.
- The I/O voltages are compatible.
- The design has achieved a successful fit in the Quartus Prime software.
Refer to the Arria 10 Device Handbook and the Configuration Function column of the Pin-Out files for more information about pins and configuration modes.
- The number of I/O banks that you require depends on the memory interface width.
- The 3V I/O bank does not support dynamic OCT or calibrated OCT. To place a memory interface in a 3V I/O bank, ensure that calibrated OCT is disabled for the address/command signals, the memory clock signals, and the data bus signals, during IP generation.
- In some device packages, the number of I/O pins in some LVDS I/O banks is less that 48 pins.
Address/Command Pins Location
- All address/command pins for a controller must be in a single I/O bank.
- If your interface uses multiple I/O banks, the address/command pins must use the middle bank. If the number of banks used by the interface is even, any of the two middle I/O banks can be used for address/command pins.
- Address/command pins and data pins cannot share an I/O lane but can share an I/O bank.
- The address/command pin locations for the soft and hard memory controllers are predefined. In the External Memory Interface Pin Information for Devices spreadsheet, each index in the "Index within I/O bank" column denotes a dedicated address/command pin function for a given protocol. The index number of the pin specifies to which I/O lane the pin belongs:
- I/O lane 0—Pins with index 0 to 11
- I/O lane 1—Pins with index 12 to 23
- I/O lane 2—Pins with index 24 to 35
- I/O lane 3—Pins with index 36 to 47
- For memory topologies and protocols that require only three I/O lanes for the address/command pins, use I/O lanes 0, 1, and 2.
- Unused address/command pins in an I/O lane can be used as general-purpose I/O pins.
CK Pins Assignment
Assign the clock pin (CK pin) according to the number of I/O banks in an interface:
- The number of I/O banks is odd—assign one CK pin to the middle I/O bank.
- The number of I/O banks is even—assign the CK pin to any one of the middle two I/O banks.
Although the Fitter can automatically select the required I/O banks, Intel® recommends that you make the selection manually to reduce the pre-fit run time.
PLL Reference Clock Pin Placement
Place the PLL reference clock pin in the address/command bank. Other I/O banks may not have free pins that you can use as the PLL reference clock pin:
- If you are sharing the PLL reference clock pin between several interfaces, the I/O banks must be consecutive.
The Arria 10 External Memory Interface IP does not support PLL cascading.
RZQ Pin Placement
You may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO and VCCPT for the memory interface I/O standard in use. The recommended location is in the address/command I/O bank.
DQ and DQS Pins Assignment
Intel® recommends that you assign the DQS pins to the remaining I/O lanes in the I/O banks as required:
- Constrain the DQ and DQS signals of the same DQS group to the same I/O lane.
- DQ signals from two different DQS groups cannot be constrained to the same I/O lane.
If you do not specify the DQS pins assignment, the Fitter will automatically select the DQS pins.
Sharing an I/O Bank Across Multiple Interfaces
If you are sharing an I/O bank across multiple external memory interfaces, follow these guidelines:
- The interfaces must use the same protocol, voltage, data rate, frequency, and PLL reference clock.
- You cannot use an I/O bank as the address/command bank for more than one interface. The memory controller and sequencer cannot be shared.
- You cannot share an I/O lane. There is only one DQS input per I/O lane, and an I/O lane can only connect to one memory controller.
Ping Pong PHY Implementation
The Ping Pong PHY feature instantiates two hard memory controllers—one for the primary interface and one for the secondary interface. The hard memory controller I/O bank of the primary interface is used for address and command and is always adjacent and above the hard memory controller I/O bank of the secondary interface. All four lanes of the primary hard memory controller I/O bank are used for address and command.
When you use Ping Pong PHY, the EMIF IP exposes two independent Avalon-MM interfaces to user logic; these interfaces correspond to the two hard memory controllers inside the interface. Each Avalon-MM interface has its own set of clock and reset signals. Refer to Qsys Interfaces for more information on the additional signals exposed by Ping Pong PHY interfaces.
For more information on Ping Pong PHY in Arria 10, refer to Functional Description—Arria 10 EMIF, in this handbook. For pin allocation information for Arria 10 devices, refer to External Memory Interface Pin Information for Arria 10 Devices on www.altera.com.
Additional Requirements for DDR3 and DDR4 Ping-Pong PHY Interfaces
If you are using Ping Pong PHY with a DDR3 or DDR4 external memory interface on an Arria 10 device, follow these guidelines:
- The address and command I/O bank must not contain any DQS group.
- I/O banks that are above the address and command I/O bank must contain only data pins of the primary interface—that is, the interface with the lower DQS group indices.
- The I/O bank immediately below the address and command I/O bank must contain at least one DQS group of the secondary interface—that is, the interface with the higher DQS group indices. This I/O bank can, but is not required to, contain DQS groups of the primary interface.
- I/O banks that are two or more banks below the address and command I/O bank must contain only data pins of the secondary interface.
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