External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.6.1.4.1.2. Write Capture

During write operations, the FPGA generates a DQS strobe and a center‑aligned DQ data bus using multiple PLL-driven clock outputs. The memory device receives these signals and captures them internally. The Stratix III family contains dedicated DDIO (double data rate I/O) blocks inside the IOEs.

For write operations, the FPGA device is the transmitter and the memory device is the receiver. The memory device’s data sheet specifies data setup and data hold time requirements based on the input slew rate on the DQ/DQS pins. These requirements make up the memory sampling window, and include all timing uncertainties internal to the memory.

Output skew across the DQ and DQS output pins on the FPGA make up the TCCS specification. TCCS includes contributions from numerous internal FPGA circuits, including:

  • Location of the DQ and DQS output pins
  • Width of the DQ group
  • PLL clock uncertainties, including phase jitter between different output taps used to center-align DQS with respect to DQ
  • Clock skew across the DQ output pins, and between DQ and DQS output pins
  • Package skew on DQ and DQS output pins

Refer to the DC and Switching Characteristics chapter of the Stratix III Device Handbook for TCCS and SW specifications.

The following figure illustrates the timing budget for a write data timing path.

Figure 75. Timing Budget for Write Data Timing Path


The following table lists a write data timing analysis for a Stratix III –2 speed‑grade device interfacing with a DDR2 SDRAM component at 400 MHz. This timing analysis assumes the use of a differential DQS strobe with 2.0‑V/ns edge rates on DQS, and 1.0‑V/ns edge rate on DQ output pins. Consult your memory device’s data sheet for derated setup and hold requirements based on the DQ/DQS output edge rates from your FPGA.

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Table 499.  Write Data Timing Analysis for 400-MHz DDR2 SDRAM Stratix III Device   (1)   

Parameter

Specifications

Value (ps)

Description

Memory Specifications  (1)

tHP

1250

Average half period as specified by the memory data sheet

tDSA

250

Memory setup requirement (derated for DQ/DQS edge rates and VREF reference voltage)

tDHA

250

Memory hold requirement (derated for DQ/DQS edge rates and VREF reference voltage)

FPGA Specifications

TCCSLEAD

229

FPGA transmitter channel-to-channel skew for a given configuration (PLL setting, location, and width).

TCCSLAG

246

Board Specifications

tEXT

20

Maximum board trace variation allowed between any two signal traces (user specified parameter)

Timing Calculations

tOUTPUT_CLOCK _OFFSET

625

Output clock phase offset between DQ & DQS output clocks = 90°.

tOUTPUT_CLOCK_OFFSET = (output clock phase DQ and DQS offset x tCK)/360° = (90° x 2500)/360° = 625

TX_DVWLEAD

396

Transmitter data valid window = tOUTPUT_CLOCK_OFFSET – TCCSLEAD

TX_DVWLAG

379

Transmitter data valid window = tHP - tOUTPUT_CLOCK_OFFSET – TCCSLAG

Results

Setup margin

126

TX_DVWLEAD – tEXT – tDSA

Hold margin

109

TX_DVWLAG – tEXT – tDHA

Notes to Table:

  1. This sample calculation uses memory timing parameters from a 72-bit wide 256-MB micron MT9HTF3272AY-80E 400-MHz DDR2 SDRAM DIMM

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