External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.6.1.4.1.1. Read Capture

Memory devices provide edge-aligned DQ and DQS outputs to the FPGA during read operations. Stratix III FPGAs center-aligns the DQS strobe using static DLL-based delays. Stratix III devices use a source synchronous circuit for data capture.

When applying this methodology to read data timing, the memory device is the transmitter and the FPGA device is the receiver.

The transmitter channel-to-channel skew on outputs from the memory device is available from the corresponding device data sheet. Let us examine the TCCS parameters for a DDR2 SDRAM component.

For DQS-based capture:

  • The time between DQS strobe and latest data valid is defined as tDQSQ
  • The time between earliest data invalid and next strobe is defined as tQHS
  • Based on earlier definitions, TCCSLEAD = tDQSQ and TCCSLAG = tQHS

The sampling window at the receiver, the FPGA, includes several timing parameters:

  • Capture register micro setup and micro hold time requirements
  • DQS clock uncertainties because of DLL phase shift error and phase jitter
  • Clock skew across the DQS bus feeding DQ capture registers
  • Data skew on DQ paths from pin to input register including package skew

For TCCS and SW specifications, refer to the DC and Switching Characteristics chapter of the Stratix III Device Handbook.

The following figure shows the timing budget for a read data timing path.

Figure 74. Timing Budget for Read Data Timing Path


The following table lists a read data timing analysis for a Stratix III –2 speed‑grade device interfacing with a 400-MHz DDR2 SDRAM component.

Table 498.  Read Data Timing Analysis for Stratix III Device with a 400-MHz DDR2 SDRAM  (1)   

Parameter

Specifications

Value (ps)

Description

Memory Specifications  (1)

tHP

1250

Average half period as specified by the memory data sheet, tHP = 1/2 * tCK

tDCD

50

Duty cycle distortion = 2% × tCK = 0.02 × 2500 ps

tDQSQ

200

Skew between DQS and DQ from memory

tQHS

300

Data hold skew factor as specified by memory

FPGA Specifications

tSW_SETUP

181

FPGA sampling window specifications for a given configuration (DLL mode, width, location, and so on.)

tSW_HOLD

306

Board Specifications

tEXT

20

Maximum board trace variation allowed between any two signal traces (user specified parameter)

Timing Calculations

tDVW

710

tHP – tDCD – tDQSQ – tQHS – 2 × tEXT

tDQS_PHASE_DELAY

500

Ideal phase shift delay on DQS capture strobe

= (DLL phase resolution × number of delay stages × tCK) / 360° = (36° × 2 stages × 2500 ps)/360° = 500 ps

Results

Setup margin

99

RSKMSETUP = tDQSQ_PHASE_DELAY – tDQSQ – tSW_SETUP – tEXT

Hold margin

74

RSKMHOLD = tHP – tDCD – tDQS_PHASE_DELAY – tQHS – tSW_HOLD – tEXT

Notes to Table:

  1. This sample calculation uses memory timing parameters from a 72-bit wide 256-MB micron MT9HTF3272AY-80E 400‑MHz DDR2 SDRAM DIMM.

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