External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.5. Timing Constraint and Report Files for Stratix 10 EMIF IP

To ensure a successful external memory interface operation, the Stratix 10 EMIF IP generates two sets of files for timing constraints but in different folders and with slightly different filenames.

One set of files are used for synthesis project, which is available under the <variation_name> folder located in the main project folder while the other set of files are the example designs, located in the <variation_name>_example design\qii\ip folder.

The project folders contain the following files for timing constraints and reporting scripts:

  • <variation_name>.sdc
  • <variation_name>_ip_parameters.tcl
  • <variation_name>_parameters.tcl
  • <variation_name> _pin_map.tcl
  • <variation_name>_report_timing.tcl

<variation_name>.sdc

The <variation_name>.sdc file allows the Quartus Prime fitter to optimize timing margins with timing-driven compilation.

To analyze timing margins for all Stratix 10 external memory interface IP timing paths, run the Report DDR function in the TimeQuest Timing Analyzer.

The Stratix 10 EMIF IP uses the .sdc file for the following operations:

  • Creating clocks on PLL inputs
  • Creating generated clocks
  • Calling derive_clock_uncertainty
  • Creating a false path from a user clock to a hard memory controller clock, and vice versa
  • Setting output delays on address and command outputs (versus CK/CK# outputs)

<variation_name>_ip_parameters.tcl

The <variation_name>_ip_parameters.tcl file is a script that lists the Stratix 10 EMIF IP memory parameters and board parameters defined in the MegaWizard, which are used in the .sdc file and timing report scripts.

<variation_name>_parameters.tcl

The <variation_name>_parameters.tcl file is a script that lists the Stratix 10 EMIF IP device and speed grade dependent values, which are used in the .sdc file and report timing scripts:
  • Jitter
  • Simultaneous switching noise
  • Duty cycle distortion
  • Calibration uncertainties

<variation_name>_pin_map.tcl

The <variation_name>_pin_map.tcl file is a library of functions and procedures that the <variation_name>report_timing.tcl and <variation_name>.sdc scripts use.

<variation_name>_report_timing.tcl

The <variation_name>_report_timing.tcl file is a script that contains timing analysis flow and reports the timing slack for your variation. This script runs automatically during calibration (during static timing analysis) by sourcing the following files:

  • <variation_name>_ip_parameters.tcl
  • <variation_name>_parameters.tcl
  • <variation_name> _pin_map.tcl
  • <variation_name>_report_timing_core.tcl

You can also run <variation_name>_report_timing.tcl with the Report DDR function in the TimeQuest Timing Analyzer. This script runs for every instance of the same variation.

<variation_name>_report_timing_core.tcl

The <variation_name>_report_timing_core.tcl file is a script that <variation_name>_report_timing.tcl uses to calculate the timing slack for your variation. <variation_name>_report_timing_core.tcl runs automatically during compilation.

<variation_name>_report_io_timing.tcl

The <variation_name>_report_io_timing.tcl file is a script that contains an early I/O estimation for your external memory interface design, excluding FPGA core timing analysis. This script allows you to determine early I/O margins without having to compile your design.

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