External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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7.5.6.2. Stratix 10 EMIF IP QDR-IV Parameters: Memory

Table 424.  Group: Memory / Topology
Display Name Identifier Description
Address width MEM_QDR4_ADDR_WIDTH Number of address pins.
DINVA / DINVB width MEM_QDR4_DINV_PER_PORT_WIDTH Number of DINV pins for port A or B of the memory interface. Automatically calculated based on the DQ width per device and whether width expansion is enabled. Two memory input pins without expansion and four pins with width expansion.
DKA / DKB width MEM_QDR4_DK_PER_PORT_WIDTH Number of DK clock pairs for port A or B of the memory interface. Automatically calculated based on the DQ width per device and whether width expansion is enabled. Two memory input pins without expansion and four pins with width expansion.
DQ width per device MEM_QDR4_DQ_PER_PORT_PER_DEVICE Specifies number of DQ pins per RLDRAM3 device and number of DQ pins per port per QDR IV device. Available widths for DQ are x18 and x36.
DQA / DQB width MEM_QDR4_DQ_PER_PORT_WIDTH Number of DQ pins for port A or B of the memory interface. Automatically calculated based on the DQ width per device and whether width expansion is enabled. The interface supports a width expansion configuration up to 72-bits
QKA / QKB width MEM_QDR4_QK_PER_PORT_WIDTH Number of QK clock pairs for port A or B of the memory interface. Automatically calculated based on the DQ width per device and whether width expansion is enabled. Two memory input pins without expansion and four pins with width expansion.
Enable width expansion MEM_QDR4_WIDTH_EXPANDED Indicates whether to combine two memory devices to double the data bus width. With two devices, the interface supports a width expansion configuration up to 72-bits. For width expansion configuration, the address and control signals are routed to 2 devices.
Table 425.  Group: Memory / Configuration Register Settings
Display Name Identifier Description
ODT (Address/Command) MEM_QDR4_AC_ODT_MODE_ENUM Determines the configuration register setting that controls the address/command ODT setting.
Address bus inversion MEM_QDR4_ADDR_INV_ENA Enable address bus inversion. AINV are all active high at memory device.
ODT (Clock) MEM_QDR4_CK_ODT_MODE_ENUM Determines the configuration register setting that controls the clock ODT setting.
Data bus inversion MEM_QDR4_DATA_INV_ENA Enable data bus inversion for DQ pins. DINVA[1:0] and DINVB[1:0] are all active high. When set to 1, the corresponding bus is inverted at memory device. If the data inversion feature is programmed to be OFF, then the DINVA/DINVB output bits will always be driven to 0.
ODT (Data) MEM_QDR4_DATA_ODT_MODE_ENUM Determines the configuration register setting that controls the data ODT setting.
Output drive (pull-down) MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM Determines the configuration register setting that controls the pull-down output drive setting.
Output drive (pull-up) MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM Determines the configuration register setting that controls the pull-up output drive setting.

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