External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents Stratix 10 EMIF IP QDR-IV Parameters: Controller

Table 434.  Group: Controller
Display Name Identifier Description
Generate power-of-2 data bus widths for Qsys CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS If enabled, the Avalon data bus width is rounded down to the nearest power-of-2. The width of the symbols within the data bus is also rounded down to the nearest power-of-2. You should only enable this option if you know you will be connecting the memory interface to Qsys interconnect components that require the data bus and symbol width to be a power-of-2. If this option is enabled, you cannot utilize the full density of the memory device. For example, in x36 data width upon selecting this parameter, will define the Avalon data bus to 256-bit. This will ignore the upper 4-bit of data width.
Maximum Avalon-MM burst length CTRL_QDR4_AVL_MAX_BURST_COUNT Specifies the maximum burst length on the Avalon-MM bus. This will be used to configure the FIFOs to be able to manage the maximum data burst. More core logic will require for increase in FIFO length.

Did you find the information on this page useful?

Characters remaining:

Feedback Message