External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.5.7.5. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Board

Table 456.  Group: Board / Intersymbol Interference/Crosstalk
Display Name Identifier Description
Address and command ISI/crosstalk BOARD_QDR2_USER_AC_ISI_NS The address and command window reduction due to ISI and crosstalk effects. The number to be entered is the total of the measured loss of margin on the setup side plus the measured loss of margin on the hold side. Refer to the EMIF Simulation Guidance wiki page for additional information.
CQ/CQ# ISI/crosstalk BOARD_QDR2_USER_RCLK_ISI_NS CQ/CQ# ISI/crosstalk describes the reduction of the read data window due to intersymbol interference and crosstalk effects on the CQ/CQ# signal when driven by the memory device during a read. The number to be entered in the Quartus Prime software is the total of the measured loss of margin on the setup side plus the measured loss of margin on the hold side. Refer to the EMIF Simulation Guidance wiki page for additional information.
Read Q ISI/crosstalk BOARD_QDR2_USER_RDATA_ISI_NS Read Q ISI/crosstalk describes the reduction of the read data window due to intersymbol interference and crosstalk effects on the CQ/CQ# signal when driven by the memory device during a read. The number to be entered in the Quartus Prime software is the total of the measured loss of margin on the setup side plus the measured loss of margin on the hold side. Refer to the EMIF Simulation Guidance wiki page for additional information.
K/K# ISI/crosstalk BOARD_QDR2_USER_WCLK_ISI_NS K/K# ISI/crosstalk describes the reduction of the write data window due to intersymbol interference and crosstalk effects on the K/K# signal when driven by the FPGA during a write. The number to be entered in the Quartus Prime software is the total of the measured loss of margin on the setup side plus the measured loss of margin on the hold side. Refer to the EMIF Simulation Guidance wiki page for additional information.
Write D ISI/crosstalk BOARD_QDR2_USER_WDATA_ISI_NS Write D ISI/crosstalk describes the reduction of the write data window due to intersymbol interference and crosstalk effects on the signal when driven by driven by the FPGA during a write. The number to be entered in the Quartus Prime software is the total of the measured loss of margin on the setup side plus the measured loss of margin on the hold side. Refer to the EMIF Simulation Guidance wiki page for additional information.
Use default ISI/crosstalk values BOARD_QDR2_USE_DEFAULT_ISI_VALUES You can enable this option to use default intersymbol interference and crosstalk values for your topology. Note that the default values are not optimized for your board. For optimal signal integrity, it is recommended that you do not enable this parameter, but instead perform I/O simulation using IBIS models and Hyperlynx*, and manually enter values based on your simulation results, instead of using the default values.
Table 457.  Group: Board / Board and Package Skews
Display Name Identifier Description
Average delay difference between address/command and K BOARD_QDR2_AC_TO_K_SKEW_NS This parameter refers to the average delay difference between the Address/Command signals and the K signal, calculated by averaging the longest and smallest Address/Command trace delay minus the maximum K trace delay. Positive values represent address and command signals that are longer than K signals and negative values represent address and command signals that are shorter than K signals.
Maximum board skew within D group BOARD_QDR2_BRD_SKEW_WITHIN_D_NS This parameter refers to the largest skew between all D and BWS# signals in a D group. D pins are used for driving data signals to the memory device during a write operation. BWS# pins are used as Byte Write Select signals to control which byte(s) are written to the memory during a write operation. Users should enter their board skew only. Package skew will be calculated automatically, based on the memory interface configuration, and added to this value. This value affects the read capture and write margins.a
Maximum board skew within Q group BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS This parameter describes the largest skew between all Q signals in a Q group. Q pins drive the data signals from the memory to the FPGA when the read operation is active. Users should enter their board skew only. Package skew will be calculated automatically, based on the memory interface configuration, and added to this value. This value affects the read capture and write margins.
Package deskewed with board layout (address/command bus) BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED Enable this parameter if you are compensating for package skew on the address, command, control, and memory clock buses in the board layout. Include package skew in calculating the following board skew parameters.
Package deskewed with board layout (D group) BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED If you are compensating for package skew on the D and BWS# signals in the board layout (hence checking the box here), please include package skew in calculating the following board skew parameters.
Package deskewed with board layout (Q group) BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED If you are compensating for package skew on the Q bus in the board layout (hence checking the box here), please include package skew in calculating the following board skew parameters.
Maximum K delay to device BOARD_QDR2_MAX_K_DELAY_NS The maximum K delay to device refers to the delay of the longest K trace from the FPGA to any device
Maximum system skew within address/command bus BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS Maximum system skew within address/command bus refers to the largest skew between the address and command signals.

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