External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.5.7.4. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Timing

These parameters should be read from the table in the datasheet associated with the speed bin of the memory device (not necessarily the frequency at which the interface is running).
Table 455.  Group: Mem Timing / Parameters dependent on Speed Bin
Display Name Identifier Description
Internal Jitter MEM_QDR2_INTERNAL_JITTER_NS QDRII internal jitter.
Speed bin MEM_QDR2_SPEEDBIN_ENUM The speed grade of the memory device used. This parameter refers to the maximum rate at which the memory device is specified to run.
tCCQO MEM_QDR2_TCCQO_NS tCCQO describes the skew between the rising edge of the C clock to the rising edge of the echo clock (CQ) in QDRII memory devices.
tCQDOH MEM_QDR2_TCQDOH_NS tCQDOH refers to the minimum time expected between the echo clock (CQ or CQ#) edge and the last of the valid Read data (Q).
tCQD MEM_QDR2_TCQD_NS tCQD refers to the maximum time expected between an echo clock edge and valid data on the Read Data bus (Q).
tCQH MEM_QDR2_TCQH_NS tCQH describes the time period during which the echo clock (CQ, #CQ) is considered logically high.
tHA MEM_QDR2_THA_NS tHA refers to the hold time after the rising edge of the clock (K) to the address and command control bus (A). The address and command control bus must remain stable for at least tHA after the rising edge of K.
tHD MEM_QDR2_THD_NS tHD refers to the hold time after the rising edge of the clock (K) to the data bus (D). The data bus must remain stable for at least tHD after the rising edge of K.
tRL MEM_QDR2_TRL_CYC tRL refers to the QDR memory specific read latency. This parameter describes the length of time after a Read command has been registered on the rising edge of the Write Clock (K) at the QDR memory before the first piece of read data (Q) can be expected at the output of the memory. It is measured in Write Clock (K) cycles. The Read Latency is specific to a QDR memory device and cannot be modified to a different value. The Read Latency (tRL) can have the following values: 1.5, 2, 2,5 clk cycles.
tSA MEM_QDR2_TSA_NS tSA refers to the setup time for the address and command bus (A) before the rising edge of the clock (K). The address and command bus must be stable for at least tSA before the rising edge of K.
tSD MEM_QDR2_TSD_NS tSD refers to the setup time for the data bus (D) before the rising edge of the clock (K). The data bus must be stable for at least tSD before the rising edge of K.
tWL MEM_QDR2_TWL_CYC tWL refers to the write latency requirement at the QDR memory. This parameter describes the length of time after a Write command has been registered at the memory on the rising edge of the Write clock (K) before the memory expects the Write Data (D). It is measured in (K) clock cycles and is usually 1.

Did you find the information on this page useful?

Characters remaining:

Feedback Message