External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.5.7.2. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Memory

Table 449.  Group: Memory / Topology
Display Name Identifier Description
Address width MEM_QDR2_ADDR_WIDTH Number of address pins.
Burst length MEM_QDR2_BL Burst length of the memory device.
Enable BWS# pins MEM_QDR2_BWS_EN Indicates whether the interface uses the BWS#( Byte Write Select) pins. If enabled, 1 BWS# pin for every 9 D pins will be added.
BWS# width MEM_QDR2_BWS_N_WIDTH Number of BWS# (Byte Write Select) pins of the memory interface. Automatically calculated based on the data width per device and whether width expansion is enabled. BWS# pins are used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered.
CQ width MEM_QDR2_CQ_WIDTH Width of the CQ (read strobe) clock on the memory device.
Data width per device MEM_QDR2_DATA_PER_DEVICE Number of D and Q pins per QDR II device.
Data width MEM_QDR2_DATA_WIDTH Number of D and Q pins of the memory interface. Automatically calculated based on the D and Q width per device and whether width expansion is enabled.
K width MEM_QDR2_K_WIDTH Width of the K (address, command and write strobe) clock on the memory device.
Enable width expansion MEM_QDR2_WIDTH_EXPANDED Indicates whether to combine two memory devices to double the data bus width. With two devices, the interface supports a width expansion configuration up to 72-bits. For width expansion configuration, the address and control signals are routed to 2 devices.

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