External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.5.4.2. Stratix 10 EMIF IP DDR3 Parameters: Memory

Table 360.  Group: Memory / Topology
Display Name Identifier Description
DQS group of ALERT# MEM_DDR3_ALERT_N_DQS_GROUP Select the DQS group with which the ALERT# pin is placed.
ALERT# pin placement MEM_DDR3_ALERT_N_PLACEMENT_ENUM Specifies placement for the mem_alert_n signal. If you select "I/O Lane with Address/Command Pins", you can pick the I/O lane and pin index in the add/cmd bank with the subsequent drop down menus. If you select "I/O Lane with DQS Group", you can specify the DQS group with which to place the mem_alert_n pin. If you select "Automatically select a location", the IP automatically selects a pin for the mem_alert_n signal. If you select this option, no additional location constraints can be applied to the mem_alert_n pin, or a fitter error will result during compilation. For optimum signal integrity, you should choose "I/O Lane with Address/Command Pins". For interfaces containing multiple memory devices, it is recommended to connect the ALERT# pins together to the ALERT#pin on the FPGA.
Bank address width MEM_DDR3_BANK_ADDR_WIDTH Specifies the number of bank address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of bank address pins needed for access to all available banks.
Number of clocks MEM_DDR3_CK_WIDTH Specifies the number of CK/CK# clock pairs exposed by the memory interface. Usually more than 1 pair is required for RDIMM/LRDIMM formats. The value of this parameter depends on the memory device selected; refer to the data sheet for your memory device.
Column address width MEM_DDR3_COL_ADDR_WIDTH Specifies the number of column address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of address pins needed for access to all available columns.
Number of chip selects per DIMM MEM_DDR3_CS_PER_DIMM Specifies the number of chip selects per DIMM.
Number of chip selects MEM_DDR3_DISCRETE_CS_WIDTH Specifies the total number of chip selects in the interface, up to a maximum of 4. This parameter applies to discreet components only.
Enable DM pins MEM_DDR3_DM_EN Indicates whether the interface uses data mask (DM) pins. This feature allows specified portions of the data bus to be written to memory (not available in x4 mode). One DM pin exists per DQS group
Number of DQS groups MEM_DDR3_DQS_WIDTH Specifies the total number of DQS groups in the interface. This value is automatically calculated as the DQ width divided by the number of DQ pins per DQS group.
DQ pins per DQS group MEM_DDR3_DQ_PER_DQS Specifies the total number of DQ pins per DQS group.
DQ width MEM_DDR3_DQ_WIDTH Specifies the total number of data pins in the interface. The maximum supported width is 144, or 72 in Ping Pong PHY mode.
Memory format MEM_DDR3_FORMAT_ENUM Specifies the format of the external memory device. The following formats are supported: Component - a Discrete memory device; UDIMM - Unregistered/Unbuffered DIMM where address/control, clock, and data are unbuffered; RDIMM - Registered DIMM where address/control and clock are buffered; LRDIMM - Load Reduction DIMM where address/control, clock, and data are buffered. LRDIMM reduces the load to increase memory speed and supports higher densities than RDIMM; SODIMM - Small Outline DIMM is similar to UDIMM but smaller in size and is typically used for systems with limited space. Some memory protocols may not be available in all formats.
Number of DIMMs MEM_DDR3_NUM_OF_DIMMS Total number of DIMMs.
Number of physical ranks per DIMM MEM_DDR3_RANKS_PER_DIMM Number of ranks per DIMM. For LRDIMM, this represents the number of physical ranks on the DIMM behind the memory buffer
Number of rank multiplication pins MEM_DDR3_RM_WIDTH Number of rank multiplication pins used to access all physical ranks on an LRDIMM. Rank multiplication is a ratio between the number of physical ranks for an LRDIMM and the number of logical ranks for the controller. These pins should be connected to CS#[2] and/or CS#[3] of all LRDIMMs in the system
Row address width MEM_DDR3_ROW_ADDR_WIDTH Specifies the number of row address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of address pins needed for access to all available rows.
Table 361.  Group: Memory / Latency and Burst
Display Name Identifier Description
Memory additive CAS latency setting MEM_DDR3_ATCL_ENUM Determines the posted CAS additive latency of the memory device. Enable this feature to improve command and bus efficiency, and increase system bandwidth.
Burst Length MEM_DDR3_BL_ENUM Specifies the DRAM burst length which determines how many consecutive addresses should be accessed for a given read/write command.
Read Burst Type MEM_DDR3_BT_ENUM Indicates whether accesses within a given burst are in sequential or interleaved order. Select sequential if you are using the Intel-provided memory controller.
Memory CAS latency setting MEM_DDR3_TCL Specifies the number of clock cycles between the read command and the availability of the first bit of output data at the memory device. Overall read latency equals the additive latency (AL) + the CAS latency (CL). Overall read latency depends on the memory device selected; refer to the datasheet for your device.
Memory write CAS latency setting MEM_DDR3_WTCL Specifies the number of clock cycles from the release of internal write to the latching of the first data in at the memory device. This value depends on the memory device selected; refer to the datasheet for your device.
Table 362.  Group: Memory / Mode Register Settings
Display Name Identifier Description
Auto self-refresh method MEM_DDR3_ASR_ENUM Indicates whether to enable or disable auto self-refresh. Auto self-refresh allows the controller to issue self-refresh requests, rather than manually issuing self-refresh in order for memory to retain data.
DDR3 LRDIMM additional control words MEM_DDR3_LRDIMM_EXTENDED_CONFIG Each 4-bit setting can be obtained from the manufacturer's data sheet and should be entered in hexadecimal, starting with BC0F on the left and ending with BC00 on the right
DLL precharge power down MEM_DDR3_PD_ENUM Specifies whether the DLL in the memory device is off or on during precharge power-down
DDR3 RDIMM/LRDIMM control words MEM_DDR3_RDIMM_CONFIG Each 4-bit/8-bit setting can be obtained from the manufacturer's data sheet and should be entered in hexadecimal, starting with the 8-bit setting RCBx on the left and continuing to RC1x followed by the 4-bit setting RCOF and ending with RC00 on the right
Self-refresh temperature MEM_DDR3_SRT_ENUM Specifies the self-refresh temperature as "Normal" or "Extended" mode. More information on Normal and Extended temperature modes can be found in the memory device datasheet.

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