External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents
1. Planning Pin and FPGA Resources 2. DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines 3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines 4. LPDDR2 and LPDDR3 SDRAM Board Design Guidelines 5. RLDRAM II and RLDRAM 3 Board Design Guidelines 6. QDR II and QDR-IV SRAM Board Design Guidelines 7. Implementing and Parameterizing Memory IP 8. Simulating Memory IP 9. Analyzing Timing of Memory IP 10. Debugging Memory IP 11. Optimizing the Controller 12. PHY Considerations 13. Power Estimation Methods for External Memory Interfaces
1. Planning Pin and FPGA Resources
1.1. Interface Pins 1.2. Guidelines for Intel® Arria® 10 External Memory Interface IP 1.3. Guidelines for Intel® Stratix® 10 External Memory Interface IP 1.4. Guidelines for UniPHY-based External Memory Interface IP 1.5. Using PLL Guidelines 1.6. PLL Cascading 1.7. DLL 1.8. Other FPGA Resources 1.9. Document Revision History
1.1. Interface Pins
1.1.1. Estimating Pin Requirements 1.1.2. DDR, DDR2, DDR3, and DDR4 SDRAM Clock Signals 1.1.3. DDR, DDR2, DDR3, and DDR4 SDRAM Command and Address Signals 1.1.4. DDR, DDR2, DDR3, and DDR4 SDRAM Data, Data Strobes, DM/DBI, and Optional ECC Signals 1.1.5. DDR, DDR2, DDR3, and DDR4 SDRAM DIMM Options 1.1.6. QDR II, QDR II+, and QDR II+ Xtreme SRAM Clock Signals 1.1.7. QDR II, QDR II+ and QDR II+ Xtreme SRAM Command Signals 1.1.8. QDR II, QDR II+ and QDR II+ Xtreme SRAM Address Signals 1.1.9. QDR II, QDR II+ and QDR II+ Xtreme SRAM Data, BWS, and QVLD Signals 1.1.10. QDR IV SRAM Clock Signals 1.1.11. QDR IV SRAM Commands and Addresses, AP, and AINV Signals 1.1.12. QDR IV SRAM Data, DINV, and QVLD Signals 1.1.13. RLDRAM II and RLDRAM 3 Clock Signals 1.1.14. RLDRAM II and RLDRAM 3 Commands and Addresses 1.1.15. RLDRAM II and RLDRAM 3 Data, DM and QVLD Signals 1.1.16. LPDDR2 and LPDDR3 Clock Signal 1.1.17. LPDDR2 and LPDDR3 Command and Address Signal 1.1.18. LPDDR2 and LPDDR3 Data, Data Strobe, and DM Signals 1.1.19. Maximum Number of Interfaces 1.1.20. OCT Support
1.1.19. Maximum Number of Interfaces
1.1.19.1. Maximum Number of DDR SDRAM Interfaces Supported per FPGA 1.1.19.2. Maximum Number of DDR2 SDRAM Interfaces Supported per FPGA 1.1.19.3. Maximum Number of DDR3 SDRAM Interfaces Supported per FPGA 1.1.19.4. Maximum Number of QDR II and QDR II+ SRAM Interfaces Supported per FPGA 1.1.19.5. Maximum Number of RLDRAM II Interfaces Supported per FPGA 1.1.19.6. Maximum Number of LPDDR2 SDRAM Interfaces Supported per FPGA
1.2. Guidelines for Intel® Arria® 10 External Memory Interface IP
1.2.1. General Pin-Out Guidelines for Arria® 10 EMIF IP 1.2.2. Resource Sharing Guidelines for Arria® 10 EMIF IP
1.3. Guidelines for Intel® Stratix® 10 External Memory Interface IP
1.3.1. General Pin-Out Guidelines for Stratix® 10 EMIF IP 1.3.2. Resource Sharing Guidelines for Stratix® 10 EMIF IP
1.4. Guidelines for UniPHY-based External Memory Interface IP
1.4.1. General Pin-out Guidelines for UniPHY-based External Memory Interface IP 1.4.2. Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II, Stratix III and Stratix IV Devices 1.4.3. Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces 1.4.4. Pin-out Rule Exceptions for QDR II and QDR II+ SRAM Burst-length-of-two Interfaces 1.4.5. Pin Connection Guidelines Tables 1.4.6. PLLs and Clock Networks
1.4.2. Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II, Stratix III and Stratix IV Devices
1.4.2.1. Timing Impact on x36 Emulation 1.4.2.2. Rules to Combine Groups 1.4.2.3. Determining the CQ/CQn Arrival Time Skew
1.4.3. Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces
1.4.3.1. Interfacing with ×9 RLDRAM II CIO Devices 1.4.3.2. Interfacing with ×18 RLDRAM II and RLDRAM 3 CIO Devices 1.4.3.3. Interfacing with RLDRAM II and RLDRAM 3 ×36 CIO Devices
1.4.5. Pin Connection Guidelines Tables
1.4.5.1. DDR3 SDRAM With Leveling Interface Pin Utilization Applicable for Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices 1.4.5.2. QDR II and QDR II+ SRAM Pin Utilization for Arria II, Arria V, Stratix III, Stratix IV, and Stratix V Devices 1.4.5.3. RLDRAM II CIO Pin Utilization for Arria II GZ, Arria V, Stratix III, Stratix IV, and Stratix V Devices  1.4.5.4. LPDDR2 Pin Utilization for Arria V, Cyclone V, and MAX 10 FPGA Devices 1.4.5.5. Additional Guidelines for Arria V GZ and Stratix V Devices 1.4.5.6. Additional Guidelines for Arria V ( Except Arria V GZ) Devices 1.4.5.7. Additional Guidelines for MAX 10 Devices 1.4.5.8. Additional Guidelines for Cyclone V Devices
1.4.6. PLLs and Clock Networks
1.4.6.1. Number of PLLs Available in Intel® Device Families 1.4.6.2. Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in Intel® Device Families 1.4.6.3. Number of Clock Networks Available in Intel® Device Families 1.4.6.4. Clock Network Usage in UniPHY-based Memory Interfaces—DDR2 and DDR3 SDRAM (1) (2) 1.4.6.5. Clock Network Usage in UniPHY-based Memory Interfaces—RLDRAM II, and QDR II and QDR II+ SRAM 1.4.6.6. PLL Usage for DDR, DDR2, and DDR3 SDRAM Without Leveling Interfaces 1.4.6.7. PLL Usage for DDR3 SDRAM With Leveling Interfaces
2. DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines
2.1. Leveling and Dynamic Termination 2.2. DDR2 Terminations and Guidelines 2.3. DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V 2.4. DDR3 and DDR4 on Arria 10 and Stratix 10 Devices 2.5. Layout Approach 2.6. Channel Signal Integrity Measurement 2.7. Design Layout Guidelines 2.8. Package Deskew 2.9. Document Revision History
2.1. Leveling and Dynamic Termination
2.1.1. Read and Write Leveling 2.1.2. Dynamic ODT 2.1.3. Dynamic On-Chip Termination 2.1.4. Dynamic On-Chip Termination in Stratix III and Stratix IV Devices 2.1.5. Dynamic OCT in Stratix V Devices 2.1.6. Dynamic On-Chip Termination (OCT) in Arria 10 and Stratix 10 Devices
2.1.3. Dynamic On-Chip Termination
2.1.3.1. FPGA Writing to Memory 2.1.3.2. FPGA Reading from Memory
2.2. DDR2 Terminations and Guidelines
2.2.1. Termination for DDR2 SDRAM 2.2.2. DDR2 Design Layout Guidelines 2.2.3. General Layout Guidelines 2.2.4. Layout Guidelines for DDR2 SDRAM Interface
2.2.1. Termination for DDR2 SDRAM
2.2.1.1. External Parallel Termination 2.2.1.2. On-Chip Termination 2.2.1.3. Recommended Termination Schemes
2.3. DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V
2.3.1. Terminations for Single-Rank DDR3 SDRAM Unbuffered DIMM 2.3.2. Terminations for Multi-Rank DDR3 SDRAM Unbuffered DIMM 2.3.3. Terminations for DDR3 SDRAM Registered DIMM 2.3.4. Terminations for DDR3 SDRAM Load-Reduced DIMM 2.3.5. Terminations for DDR3 SDRAM Components With Leveling
2.3.5. Terminations for DDR3 SDRAM Components With Leveling
2.3.5.1. DDR3 SDRAM Components With or Without Leveling
2.4. DDR3 and DDR4 on Arria 10 and Stratix 10 Devices
2.4.1. Dynamic On-Chip Termination (OCT) in Arria 10 and Stratix 10 Devices 2.4.2. Dynamic On-Die Termination (ODT) in DDR4 2.4.3. Choosing Terminations on Arria 10 Devices 2.4.4. On-Chip Termination Recommendations for DDR3 and DDR4 on Arria 10 Devices
2.6. Channel Signal Integrity Measurement
2.6.1. Importance of Accurate Channel Signal Integrity Information 2.6.2. Understanding Channel Signal Integrity Measurement 2.6.3. How to Enter Calculated Channel Signal Integrity Values 2.6.4. Guidelines for Calculating DDR3 Channel Signal Integrity 2.6.5. Guidelines for Calculating DDR4 Channel Signal Integrity
2.7. Design Layout Guidelines
2.7.1. General Layout Guidelines 2.7.2. Layout Guidelines for DDR3 and DDR4 SDRAM Interfaces 2.7.3. Length Matching Rules 2.7.4. Spacing Guidelines 2.7.5. Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits)
2.7.5. Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits)
2.7.5.1. Fly-By Network Design for Clock, Command, and Address Signals
2.8. Package Deskew
2.8.1. Package Deskew Recommendation for Stratix V Devices 2.8.2. DQ/DQS/DM Deskew 2.8.3. Address and Command Deskew 2.8.4. Package Deskew Recommendations for Arria 10 and Stratix 10 Devices 2.8.5. Deskew Example 2.8.6. Package Migration 2.8.7. Package Deskew for RLDRAM II and RLDRAM 3
3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines
3.1. General Layout Guidelines 3.2. Dual-Slot Unbuffered DDR2 SDRAM 3.3. Dual-Slot Unbuffered DDR3 SDRAM 3.4. Document Revision History
3.2. Dual-Slot Unbuffered DDR2 SDRAM
3.2.1. Overview of ODT Control 3.2.2. DIMM Configuration 3.2.3. Dual-DIMM Memory Interface with Slot 1 Populated 3.2.4. Dual-DIMM with Slot 2 Populated 3.2.5. Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated 3.2.6. Dual-DIMM DDR2 Clock, Address, and Command Termination and Topology 3.2.7. Control Group Signals 3.2.8. Clock Group Signals
3.2.3. Dual-DIMM Memory Interface with Slot 1 Populated
3.2.3.1. FPGA Writing to Memory 3.2.3.2. Write to Memory Using an ODT Setting of 150-ohm 3.2.3.3. Reading from Memory
3.2.4. Dual-DIMM with Slot 2 Populated
3.2.4.1. FPGA Writing to Memory 3.2.4.2. Write to Memory Using an ODT Setting of 150-ohm 3.2.4.3. Reading from Memory
3.2.5. Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated
3.2.5.1. FPGA Writing to Memory 3.2.5.2. Write to Memory in Slot 1 Using an ODT Setting of 75-ohm 3.2.5.3. Reading From Memory
3.3. Dual-Slot Unbuffered DDR3 SDRAM
3.3.1. Comparison of DDR3 and DDR2 DQ and DQS ODT Features and Topology 3.3.2. Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology 3.3.3. FPGA OCT Features
3.3.2. Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology
3.3.2.1. Address and Command Signals 3.3.2.2. Control Group Signals 3.3.2.3. Clock Group Signals
3.3.3. FPGA OCT Features
3.3.3.1. Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V Devices 3.3.3.2. Arria II GX Devices
4. LPDDR2 and LPDDR3 SDRAM Board Design Guidelines
4.1. LPDDR2 Guidance 4.2. LPDDR3 Guidance 4.3. Document Revision History
4.1. LPDDR2 Guidance
4.1.1. LPDDR2 SDRAM Configurations 4.1.2. OCT Signal Terminations for Arria V and Cyclone V Devices 4.1.3. General Layout Guidelines 4.1.4. LPDDR2 Layout Guidelines
4.1.2. OCT Signal Terminations for Arria V and Cyclone V Devices
4.1.2.1. Outputs from the FPGA to the LPDDR2 Component 4.1.2.2. Input to the FPGA from the LPDDR2 SDRAM Component 4.1.2.3. Termination Schemes
4.2. LPDDR3 Guidance
4.2.1. Signal Integrity, Board Skew, and Board Setting Parameters 4.2.2. LPDDR3 Layout Guidelines 4.2.3. Package Deskew
4.2.3. Package Deskew
4.2.3.1. DQ/DQS/DM Deskew 4.2.3.2. Address and Command Deskew 4.2.3.3. Package Deskew Recommendations for Arria 10 and Stratix 10 Devices 4.2.3.4. Deskew Example 4.2.3.5. Package Migration
5. RLDRAM II and RLDRAM 3 Board Design Guidelines
5.1. RLDRAM II Configurations 5.2. RLDRAM 3 Configurations 5.3. Signal Terminations 5.4. PCB Layout Guidelines 5.5. General Layout Guidelines 5.6. RLDRAM II and RLDRAM 3 Layout Guidelines 5.7. Layout Approach 5.8. Package Deskew for RLDRAM II and RLDRAM 3 5.9. Document Revision History
5.3. Signal Terminations
5.3.1. Input to the FPGA from the RLDRAM Components 5.3.2. Outputs from the FPGA to the RLDRAM II and RLDRAM 3 Components 5.3.3. RLDRAM II Termination Schemes 5.3.4. RLDRAM 3 Termination Schemes
5.7. Layout Approach
5.7.1. Arria V and Stratix V Board Setting Parameters 5.7.2. Arria 10 Board Setting Parameters
6. QDR II and QDR-IV SRAM Board Design Guidelines
6.1. QDR II SRAM Configurations 6.2. Signal Terminations 6.3. General Layout Guidelines 6.4. QDR II Layout Guidelines 6.5. QDR II SRAM Layout Approach 6.6. Package Deskew for QDR II and QDR-IV 6.7. QDR-IV Layout Approach 6.8. QDR-IV Layout Guidelines 6.9. Document Revision History
6.2. Signal Terminations
6.2.1. Output from the FPGA to the QDR II SRAM Component 6.2.2. Input to the FPGA from the QDR II SRAM Component 6.2.3. Termination Schemes
7. Implementing and Parameterizing Memory IP
7.1. Installing and Licensing IP Cores 7.2. Design Flow 7.3. UniPHY-Based External Memory Interface IP 7.4. Intel® Arria® 10 External Memory Interface IP 7.5. Intel® Stratix® 10 External Memory Interface IP 7.6. Document Revision History
7.2. Design Flow
7.2.1. IP Catalog Design Flow 7.2.2. Qsys System Integration Tool Design Flow
7.2.1. IP Catalog Design Flow
7.2.1.1. IP Catalog and Parameter Editor 7.2.1.2. Specifying Parameters for the IP Catalog Flow 7.2.1.3. Using Example Designs 7.2.1.4. Constraining the Design 7.2.1.5. Compiling the Design
7.2.1.4. Constraining the Design
7.2.1.4.1. Adding Pins and DQ Group Assignments
7.2.2. Qsys System Integration Tool Design Flow
7.2.2.1. Specify Parameters for the Qsys Flow 7.2.2.2. Completing the Qsys System
7.3. UniPHY-Based External Memory Interface IP
7.3.1. Qsys Interfaces 7.3.2. Generated Files for Memory Controllers with the UniPHY IP 7.3.3. Parameterizing Memory Controllers 7.3.4. Board Settings 7.3.5. Controller Settings for UniPHY IP 7.3.6. Diagnostics for UniPHY IP
7.3.1. Qsys Interfaces
7.3.1.1. DDR2 SDRAM Controller with UniPHY Interfaces 7.3.1.2. DDR3 SDRAM Controller with UniPHY Interfaces 7.3.1.3. LPDDR2 SDRAM Controller with UniPHY Interfaces 7.3.1.4. QDR II and QDR II+ SRAM Controller with UniPHY Interfaces 7.3.1.5. RLDRAM II Controller with UniPHY Interfaces 7.3.1.6. RLDRAM 3 UniPHY Interface
7.3.3. Parameterizing Memory Controllers
7.3.3.1. PHY Settings for UniPHY IP 7.3.3.2. Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM for UniPHY IP 7.3.3.3. Memory Parameters for QDR II and QDR II+ SRAM for UniPHY IP 7.3.3.4. Memory Parameters for RLDRAM II for UniPHY IP 7.3.3.5. Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM for UniPHY IP 7.3.3.6. Memory Timing Parameters for QDR II and QDR II+ SRAM for UniPHY IP 7.3.3.7. Memory Timing Parameters for RLDRAM II for UniPHY IP 7.3.3.8. Memory Parameters for RLDRAM 3 for UniPHY IP
7.3.3.2. Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM for UniPHY IP
7.3.3.2.1. Memory Initialization Options for DDR2 7.3.3.2.2. Memory Initialization Options for DDR3 7.3.3.2.3. Memory Initialization Options for LPDDR2
7.3.4. Board Settings
7.3.4.1. Setup and Hold Derating for UniPHY IP 7.3.4.2. Intersymbol Interference Channel Signal Integrity for UniPHY IP 7.3.4.3. Board Skews for UniPHY IP
7.3.4.3. Board Skews for UniPHY IP
7.3.4.3.1. Board Skew Parameters for LPDDR2/DDR2/DDR3 SDRAM 7.3.4.3.2. Board Skew Parameters for QDR II and QDR II+ 7.3.4.3.3. Board Skew parameters for RLDRAM II and RLDRAM 3
7.4. Intel® Arria® 10 External Memory Interface IP
7.4.1. Qsys Interfaces 7.4.2. Generated Files for Arria® 10 External Memory Interface IP 7.4.3. Arria® 10 EMIF IP DDR4 Parameters 7.4.4. Arria® 10 EMIF IP DDR3 Parameters 7.4.5. Arria® 10 EMIF IP LPDDR3 Parameters 7.4.6. Arria® 10 EMIF IP QDR-IV Parameters 7.4.7. Arria® 10 EMIF IP QDR II/II+/II+ Xtreme Parameters 7.4.8. Arria® 10 EMIF IP RLDRAM 3 Parameters 7.4.9. Equations for Arria® 10 EMIF IP Board Skew Parameters
7.4.3. Arria® 10 EMIF IP DDR4 Parameters
7.4.3.1. Arria 10 EMIF IP DDR4 Parameters: General 7.4.3.2. Arria 10 EMIF IP DDR4 Parameters: Memory 7.4.3.3. Arria 10 EMIF IP DDR4 Parameters: Mem I/O 7.4.3.4. Arria 10 EMIF IP DDR4 Parameters: FPGA I/O 7.4.3.5. Arria 10 EMIF IP DDR4 Parameters: Mem Timing 7.4.3.6. Arria 10 EMIF IP DDR4 Parameters: Board 7.4.3.7. Arria 10 EMIF IP DDR4 Parameters: Controller 7.4.3.8. Arria 10 EMIF IP DDR4 Parameters: Diagnostics 7.4.3.9. Arria 10 EMIF IP DDR4 Parameters: Example Designs 7.4.3.10. About Memory Presets 7.4.3.11. x4 Mode for Arria 10 External Memory Interface 7.4.3.12. Additional Notes About Parameterizing Arria 10 EMIF IP for HPS
7.4.4. Arria® 10 EMIF IP DDR3 Parameters
7.4.4.1. Arria 10 EMIF IP DDR3 Parameters: General 7.4.4.2. Arria 10 EMIF IP DDR3 Parameters: Memory 7.4.4.3. Arria 10 EMIF IP DDR3 Parameters: Mem I/O 7.4.4.4. Arria 10 EMIF IP DDR3 Parameters: FPGA I/O 7.4.4.5. Arria 10 EMIF IP DDR3 Parameters: Mem Timing 7.4.4.6. Arria 10 EMIF IP DDR3 Parameters: Board 7.4.4.7. Arria 10 EMIF IP DDR3 Parameters: Controller 7.4.4.8. Arria 10 EMIF IP DDR3 Parameters: Diagnostics 7.4.4.9. Arria 10 EMIF IP DDR3 Parameters: Example Designs 7.4.4.10. About Memory Presets 7.4.4.11. x4 Mode for Arria 10 External Memory Interface 7.4.4.12. Additional Notes About Parameterizing Arria 10 EMIF IP for HPS
7.4.5. Arria® 10 EMIF IP LPDDR3 Parameters
7.4.5.1. Arria 10 EMIF IP LPDDR3 Parameters: General 7.4.5.2. Arria 10 EMIF IP LPDDR3 Parameters: Memory 7.4.5.3. Arria 10 EMIF IP LPDDR3 Parameters: FPGA I/O 7.4.5.4. Arria 10 EMIF IP LPDDR3 Parameters: Mem Timing 7.4.5.5. Arria 10 EMIF IP LPDDR3 Parameters: Board 7.4.5.6. Arria 10 EMIF IP LPDDR3 Parameters: Controller 7.4.5.7. Arria 10 EMIF IP LPDDR3 Parameters: Diagnostics 7.4.5.8. Arria 10 EMIF IP LPDDR3 Parameters: Example Designs 7.4.5.9. About Memory Presets
7.4.6. Arria® 10 EMIF IP QDR-IV Parameters
7.4.6.1. Arria 10 EMIF IP QDR-IV Parameters: General 7.4.6.2. Arria 10 EMIF IP QDR-IV Parameters: Memory 7.4.6.3. Arria 10 EMIF IP QDR-IV Parameters: FPGA I/O 7.4.6.4. Arria 10 EMIF IP QDR-IV Parameters: Mem Timing 7.4.6.5. Arria 10 EMIF IP QDR-IV Parameters: Board 7.4.6.6. Arria 10 EMIF IP QDR-IV Parameters: Controller 7.4.6.7. Arria 10 EMIF IP QDR-IV Parameters: Diagnostics 7.4.6.8. Arria 10 EMIF IP QDR-IV Parameters: Example Designs 7.4.6.9. About Memory Presets
7.4.7. Arria® 10 EMIF IP QDR II/II+/II+ Xtreme Parameters
7.4.7.1. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: General 7.4.7.2. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Memory 7.4.7.3. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGA I/O 7.4.7.4. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Timing 7.4.7.5. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Board 7.4.7.6. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Controller 7.4.7.7. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Diagnostics 7.4.7.8. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Example Designs 7.4.7.9. About Memory Presets
7.4.8. Arria® 10 EMIF IP RLDRAM 3 Parameters
7.4.8.1. Arria 10 EMIF IP RLDRAM 3 Parameters: General 7.4.8.2. Arria 10 EMIF IP RLDRAM 3 Parameters: Memory 7.4.8.3. Arria 10 EMIF IP RLDRAM 3 Parameters: FPGA I/O 7.4.8.4. Arria 10 EMIF IP RLDRAM 3 Parameters: Mem Timing 7.4.8.5. Arria 10 EMIF IP RLDRAM 3 Parameters: Board 7.4.8.6. Arria 10 EMIF IP RLDRAM 3 Parameters: Diagnostics 7.4.8.7. Arria 10 EMIF IP RLDRAM 3 Parameters: Example Designs 7.4.8.8. About Memory Presets
7.4.9. Equations for Arria® 10 EMIF IP Board Skew Parameters
7.4.9.1. Equations for DDR3/DDR4/LPDDR3 Board Skew Parameters 7.4.9.2. Equations for QDR-IV Board Skew Parameters 7.4.9.3. Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Parameters 7.4.9.4. Equations for RLDRAM 3 Board Skew Parameters
7.5. Intel® Stratix® 10 External Memory Interface IP
7.5.1. Qsys Interfaces 7.5.2. Generated Files for Stratix® 10 External Memory Interface IP 7.5.3. Stratix® 10 EMIF IP DDR4 Parameters 7.5.4. Stratix® 10 EMIF IP DDR3 Parameters 7.5.5. Stratix® 10 EMIF IP LPDDR3 Parameters 7.5.6. Stratix® 10 EMIF IP QDR-IV Parameters 7.5.7. Stratix® 10 EMIF IP QDR II/II+/II+ Xtreme Parameters 7.5.8. Stratix® 10 EMIF IP RLDRAM 3 Parameters
7.5.3. Stratix® 10 EMIF IP DDR4 Parameters
7.5.3.1. Stratix 10 EMIF IP DDR4 Parameters: General 7.5.3.2. Stratix 10 EMIF IP DDR4 Parameters: Memory 7.5.3.3. Stratix 10 EMIF IP DDR4 Parameters: Mem I/O 7.5.3.4. Stratix 10 EMIF IP DDR4 Parameters: FPGA I/O 7.5.3.5. Stratix 10 EMIF IP DDR4 Parameters: Mem Timing 7.5.3.6. Stratix 10 EMIF IP DDR4 Parameters: Board 7.5.3.7. Stratix 10 EMIF IP DDR4 Parameters: Controller 7.5.3.8. Stratix 10 EMIF IP DDR4 Parameters: Diagnostics 7.5.3.9. Stratix 10 EMIF IP DDR4 Parameters: Example Designs 7.5.3.10. About Memory Presets
7.5.4. Stratix® 10 EMIF IP DDR3 Parameters
7.5.4.1. Stratix 10 EMIF IP DDR3 Parameters: General 7.5.4.2. Stratix 10 EMIF IP DDR3 Parameters: Memory 7.5.4.3. Stratix 10 EMIF IP DDR3 Parameters: Mem I/O 7.5.4.4. Stratix 10 EMIF IP DDR3 Parameters: FPGA I/O 7.5.4.5. Stratix 10 EMIF IP DDR3 Parameters: Mem Timing 7.5.4.6. Stratix 10 EMIF IP DDR3 Parameters: Board 7.5.4.7. Stratix 10 EMIF IP DDR3 Parameters: Controller 7.5.4.8. Stratix 10 EMIF IP DDR3 Parameters: Diagnostics 7.5.4.9. Stratix 10 EMIF IP DDR3 Parameters: Example Designs 7.5.4.10. About Memory Presets
7.5.5. Stratix® 10 EMIF IP LPDDR3 Parameters
7.5.5.1. Stratix 10 EMIF IP LPDDR3 Parameters: General 7.5.5.2. Stratix 10 EMIF IP LPDDR3 Parameters: Memory 7.5.5.3. Stratix 10 EMIF IP LPDDR3 Parameters: Mem I/O 7.5.5.4. Stratix 10 EMIF IP LPDDR3 Parameters: FPGA I/O 7.5.5.5. Stratix 10 EMIF IP LPDDR3 Parameters: Mem Timing 7.5.5.6. Stratix 10 EMIF IP LPDDR3 Parameters: Board 7.5.5.7. Stratix 10 EMIF IP LPDDR3 Parameters: Controller 7.5.5.8. Stratix 10 EMIF IP LPDDR3 Parameters: Diagnostics 7.5.5.9. Stratix 10 EMIF IP LPDDR3 Parameters: Example Designs 7.5.5.10. About Memory Presets
7.5.6. Stratix® 10 EMIF IP QDR-IV Parameters
7.5.6.1. Stratix 10 EMIF IP QDR-IV Parameters: General 7.5.6.2. Stratix 10 EMIF IP QDR-IV Parameters: Memory 7.5.6.3. Stratix 10 EMIF IP QDR-IV Parameters: FPGA I/O 7.5.6.4. Stratix 10 EMIF IP QDR-IV Parameters: Mem Timing 7.5.6.5. Stratix 10 EMIF IP QDR-IV Parameters: Board 7.5.6.6. Stratix 10 EMIF IP QDR-IV Parameters: Controller 7.5.6.7. Stratix 10 EMIF IP QDR-IV Parameters: Diagnostics 7.5.6.8. Stratix 10 EMIF IP QDR-IV Parameters: Example Designs 7.5.6.9. About Memory Presets
7.5.7. Stratix® 10 EMIF IP QDR II/II+/II+ Xtreme Parameters
7.5.7.1. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: General 7.5.7.2. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Memory 7.5.7.3. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGA I/O 7.5.7.4. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Timing 7.5.7.5. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Board 7.5.7.6. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Controller 7.5.7.7. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Diagnostics 7.5.7.8. Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Example Designs 7.5.7.9. About Memory Presets
7.5.8. Stratix® 10 EMIF IP RLDRAM 3 Parameters
7.5.8.1. Stratix 10 EMIF IP RLDRAM 3 Parameters: General 7.5.8.2. Stratix 10 EMIF IP RLDRAM 3 Parameters: Memory 7.5.8.3. Stratix 10 EMIF IP RLDRAM 3 Parameters: FPGA I/O 7.5.8.4. Stratix 10 EMIF IP RLDRAM 3 Parameters: Mem Timing 7.5.8.5. Stratix 10 EMIF IP RLDRAM 3 Parameters: Board 7.5.8.6. Stratix 10 EMIF IP RLDRAM 3 Parameters: Diagnostics 7.5.8.7. Stratix 10 EMIF IP RLDRAM 3 Parameters: Example Designs 7.5.8.8. About Memory Presets
8. Simulating Memory IP
8.1. Simulation Options 8.2. Simulation Walkthrough with UniPHY IP 8.3. Simulation Walkthrough with Arria® 10 EMIF IP 8.4. Simulation Walkthrough with Stratix® 10 EMIF IP 8.5. Document Revision History
8.2. Simulation Walkthrough with UniPHY IP
8.2.1. Simulation Scripts 8.2.2. Preparing the Vendor Memory Model 8.2.3. Functional Simulation with Verilog HDL 8.2.4. Functional Simulation with VHDL 8.2.5. Simulating the Example Design 8.2.6. UniPHY Abstract PHY Simulation 8.2.7. PHY-Only Simulation 8.2.8. Post-fit Functional Simulation 8.2.9. Simulation Issues
8.2.8. Post-fit Functional Simulation
8.2.8.1. Running Post-fit Simulation
8.3. Simulation Walkthrough with Arria® 10 EMIF IP
8.3.1. Skip Calibration Versus Full Calibration 8.3.2. Arria® 10 Abstract PHY Simulation 8.3.3. Simulation Scripts 8.3.4. Functional Simulation with Verilog HDL 8.3.5. Functional Simulation with VHDL 8.3.6. Simulating the Example Design
8.4. Simulation Walkthrough with Stratix® 10 EMIF IP
8.4.1. Skip Calibration Versus Full Calibration 8.4.2. Simulation Scripts 8.4.3. Functional Simulation with Verilog HDL 8.4.4. Functional Simulation with VHDL 8.4.5. Simulating the Example Design
9. Analyzing Timing of Memory IP
9.1. Memory Interface Timing Components 9.2. FPGA Timing Paths 9.3. Timing Constraint and Report Files for UniPHY IP 9.4. Timing Constraint and Report Files for Arria 10 EMIF IP 9.5. Timing Constraint and Report Files for Stratix 10 EMIF IP 9.6. Timing Analysis Description 9.7. Timing Report DDR 9.8. Report SDC 9.9. Calibration Effect in Timing Analysis 9.10. Timing Model Assumptions and Design Rules 9.11. Common Timing Closure Issues 9.12. Optimizing Timing 9.13. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs 9.14. Early I/O Timing Estimation for Arria 10 EMIF IP 9.15. Early I/O Timing Estimation for Stratix 10 EMIF IP 9.16. Performing I/O Timing Analysis 9.17. Document Revision History
9.1. Memory Interface Timing Components
9.1.1. Source-Synchronous Paths 9.1.2. Calibrated Paths 9.1.3. Internal FPGA Timing Paths 9.1.4. Other FPGA Timing Parameters
9.2. FPGA Timing Paths
9.2.1. Arria II Device PHY Timing Paths 9.2.2. Stratix III and Stratix IV PHY Timing Paths 9.2.3. Arria V, Arria V GZ, Arria 10, Cyclone V, and Stratix V Timing paths
9.6. Timing Analysis Description
9.6.1. UniPHY IP Timing Analysis 9.6.2. Timing Analysis Description for Arria 10 EMIF IP 9.6.3. Timing Analysis Description for Stratix 10 EMIF IP
9.6.1. UniPHY IP Timing Analysis
9.6.1.1. Address and Command 9.6.1.2. PHY or Core 9.6.1.3. PHY or Core Reset 9.6.1.4. Read Capture and Write 9.6.1.5. Read Resynchronization 9.6.1.6. DQS versus CK—Arria II GX and Cyclone IV Devices 9.6.1.7. Write Leveling tDQSS 9.6.1.8. Write Leveling tDSH/tDSS 9.6.1.9. DK versus CK (RLDRAM II with UniPHY) 9.6.1.10. Bus Turnaround Time
9.6.1.4. Read Capture and Write
9.6.1.4.1. Stratix III 9.6.1.4.2. Arria II, Arria V, Cyclone V, Stratix IV and Stratix V
9.6.2. Timing Analysis Description for Arria 10 EMIF IP
9.6.2.1. PHY or Core 9.6.2.2. I/O Timing
9.6.2.2. I/O Timing
9.6.2.2.1. Read Capture 9.6.2.2.2. Write 9.6.2.2.3. Address and Command 9.6.2.2.4. DQS Gating / Postamble 9.6.2.2.5. Write Leveling
9.6.3. Timing Analysis Description for Stratix 10 EMIF IP
9.6.3.1. PHY or Core 9.6.3.2. I/O Timing
9.6.3.2. I/O Timing
9.6.3.2.1. Read Capture 9.6.3.2.2. Write 9.6.3.2.3. Address and Command 9.6.3.2.4. DQS Gating / Postamble 9.6.3.2.5. Write Leveling
9.9. Calibration Effect in Timing Analysis
9.9.1. Calibration Emulation for Calibrated Path 9.9.2. Calibration Error or Quantization Error 9.9.3. Calibration Uncertainties 9.9.4. Memory Calibration
9.10. Timing Model Assumptions and Design Rules
9.10.1. Memory Clock Output Assumptions 9.10.2. Write Data Assumptions 9.10.3. Read Data Assumptions 9.10.4. DLL Assumptions 9.10.5. PLL and Clock Network Assumptions for Stratix III Devices
9.10.1. Memory Clock Output Assumptions
9.10.1.1. Memory Clock Assumptions for Stratix III Devices
9.10.2. Write Data Assumptions
9.10.2.1. Write Data Assumptions for Stratix III Devices
9.10.3. Read Data Assumptions
9.10.3.1. Read Data Assumptions for Stratix III Devices
9.11. Common Timing Closure Issues
9.11.1. Missing Timing Margin Report 9.11.2. Incomplete Timing Margin Report 9.11.3. Read Capture Timing 9.11.4. Write Timing 9.11.5. Address and Command Timing 9.11.6. PHY Reset Recovery and Removal 9.11.7. Clock-to-Strobe (for DDR and DDR2 SDRAM Only) 9.11.8. Read Resynchronization and Write Leveling Timing (for SDRAM Only)
9.13. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs
9.13.1. Multiple Chip Select Configuration Effects 9.13.2. Timing Deration using the Board Settings
9.13.1. Multiple Chip Select Configuration Effects
9.13.1.1. ISI Effects 9.13.1.2. Calibration Effects 9.13.1.3. Board Effects
9.13.2. Timing Deration using the Board Settings
9.13.2.1. Slew Rates 9.13.2.2. Slew Rate Setup, Hold, and Derating Calculation 9.13.2.3. Intersymbol Interference 9.13.2.4. Measuring Eye Reduction for Address/Command, DQ, and DQS Setup and Hold Time
9.14. Early I/O Timing Estimation for Arria 10 EMIF IP
9.14.1. Performing Early I/O Timing Analysis for Arria 10 EMIF IP
9.15. Early I/O Timing Estimation for Stratix 10 EMIF IP
9.15.1. Performing Early I/O Timing Analysis for Stratix 10 EMIF IP
9.16. Performing I/O Timing Analysis
9.16.1. Performing I/O Timing Analysis with Third-Party Simulation Tools 9.16.2. Performing Advanced I/O Timing Analysis with Board Trace Delay Model
10. Debugging Memory IP
10.1. Resource and Planning Issues 10.2. Interface Configuration Performance Issues 10.3. Functional Issue Evaluation 10.4. Timing Issue Characteristics 10.5. Verifying Memory IP Using the Signal Tap II Logic Analyzer 10.6. Hardware Debugging Guidelines 10.7. Catagorizing Hardware Issues 10.8. EMIF Debug Toolkit Overview 10.9. Document Revision History
10.1. Resource and Planning Issues
10.1.1. Dedicated IOE DQS Group Resources and Pins 10.1.2. Dedicated DLL Resources 10.1.3. Specific PLL Resources 10.1.4. Specific Global, Regional and Dual-Regional Clock Net Resources 10.1.5. Planning Your Design 10.1.6. Optimizing Design Utilization
10.2. Interface Configuration Performance Issues
10.2.1. Interface Configuration Bottleneck and Efficiency Issues
10.3. Functional Issue Evaluation
10.3.1. Correct Combination of the Quartus Prime Software and ModelSim* - Intel FPGA Edition Device Models 10.3.2. Intel® IP Memory Model 10.3.3. Vendor Memory Model 10.3.4. Insufficient Memory in Your PC 10.3.5. Transcript Window Messages 10.3.6. Passing Simulation 10.3.7. Modifying the Example Driver to Replicate the Failure
10.4. Timing Issue Characteristics
10.4.1. Evaluating FPGA Timing Issues 10.4.2. Evaluating External Memory Interface Timing Issues
10.5. Verifying Memory IP Using the Signal Tap II Logic Analyzer
10.5.1. Signals to Monitor with the Signal Tap II Logic Analyzer
10.6. Hardware Debugging Guidelines
10.6.1. Create a Simplified Design that Demonstrates the Same Issue 10.6.2. Measure Power Distribution Network 10.6.3. Measure Signal Integrity and Setup and Hold Margin 10.6.4. Vary Voltage 10.6.5. Use Freezer Spray and Heat Gun 10.6.6. Operate at a Lower Speed 10.6.7. Determine Whether the Issue Exists in Previous Versions of Software 10.6.8. Determine Whether the Issue Exists in the Current Version of Software 10.6.9. Try A Different PCB 10.6.10. Try Other Configurations 10.6.11. Debugging Checklist
10.7. Catagorizing Hardware Issues
10.7.1. Signal Integrity Issues 10.7.2. Hardware and Calibration Issues
10.7.1. Signal Integrity Issues
10.7.1.1. Characteristics of Signal Integrity Issues 10.7.1.2. Evaluating SignaI Integrity Issues
10.7.1.2. Evaluating SignaI Integrity Issues
10.7.1.2.1. Skew 10.7.1.2.2. Crosstalk 10.7.1.2.3. Power System 10.7.1.2.4. Clock Signals 10.7.1.2.5. Read Data Valid Window and Eye Diagram 10.7.1.2.6. Write Data Valid Window and Eye Diagram 10.7.1.2.7. OCT and ODT Usage
10.7.2. Hardware and Calibration Issues
10.7.2.1. Evaluating Hardware and Calibration Issues
10.7.2.1. Evaluating Hardware and Calibration Issues
10.7.2.1.1. Write Timing Margin 10.7.2.1.2. Read Timing Margin 10.7.2.1.3. Address and Command Timing Margin 10.7.2.1.4. Resynchronization Timing Margin 10.7.2.1.5. Postamble Timing Issues and Margin 10.7.2.1.6. Intermittent Issue Evaluation
11. Optimizing the Controller
11.1. Factors Affecting Efficiency 11.2. Ways to Improve Efficiency 11.3. Document Revision History
11.1. Factors Affecting Efficiency
11.1.1. Interface Standard 11.1.2. Bank Management Efficiency 11.1.3. Data Transfer
11.2. Ways to Improve Efficiency
11.2.1. DDR2 SDRAM Controller 11.2.2. Auto-Precharge Commands 11.2.3. Additive Latency 11.2.4. Bank Interleaving 11.2.5. Command Queue Look-Ahead Depth 11.2.6. Additive Latency and Bank Interleaving 11.2.7. User-Controlled Refresh 11.2.8. Frequency of Operation 11.2.9. Burst Length 11.2.10. Series of Reads or Writes 11.2.11. Data Reordering 11.2.12. Starvation Control 11.2.13. Command Reordering 11.2.14. Bandwidth 11.2.15. Efficiency Monitor
11.2.7. User-Controlled Refresh
11.2.7.1. Back-to-Back User-Controlled Refresh Usage in Arria® 10
12. PHY Considerations
12.1. Core Logic and User Interface Data Rate 12.2. Hard and Soft Memory PHY 12.3. Sequencer 12.4. PLL, DLL and OCT Resource Sharing 12.5. Pin Placement Consideration 12.6. Document Revision History
13. Power Estimation Methods for External Memory Interfaces
13.1. Performing Vector-Based Power Analysis with the Power Analyzer 13.2. Document Revision History
1. Planning Pin and FPGA Resources
2. DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines
3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines
4. LPDDR2 and LPDDR3 SDRAM Board Design Guidelines
5. RLDRAM II and RLDRAM 3 Board Design Guidelines
6. QDR II and QDR-IV SRAM Board Design Guidelines
7. Implementing and Parameterizing Memory IP
8. Simulating Memory IP
9. Analyzing Timing of Memory IP
10. Debugging Memory IP
11. Optimizing the Controller
12. PHY Considerations
13. Power Estimation Methods for External Memory Interfaces

7.5.4.5. Stratix 10 EMIF IP DDR3 Parameters: Mem Timing

These parameters should be read from the table in the datasheet associated with the speed bin of the memory device (not necessarily the frequency at which the interface is running).
Table 370.  Group: Mem Timing / Parameters dependent on Speed Bin
Display Name Identifier Description
Speed bin MEM_DDR3_SPEEDBIN_ENUM The speed grade of the memory device used. This parameter refers to the maximum rate at which the memory device is specified to run.
tDH (base) DC level MEM_DDR3_TDH_DC_MV tDH (base) DC level refers to the voltage level which the data bus must not cross during the hold window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire hold period.
tDH (base) MEM_DDR3_TDH_PS tDH (base) refers to the hold time for the Data (DQ) bus after the rising edge of CK.
tDQSCK MEM_DDR3_TDQSCK_PS tDQSCK describes the skew between the memory clock (CK) and the input data strobes (DQS) used for reads. It is the time between the rising data strobe edge (DQS, DQS#) relative to the rising CK edge.
tDQSQ MEM_DDR3_TDQSQ_PS tDQSQ describes the latest valid transition of the associated DQ pins for a READ. tDQSQ specifically refers to the DQS, DQS# to DQ skew. It is the length of time between the DQS, DQS# crossing to the last valid transition of the slowest DQ pin in the DQ group associated with that DQS strobe.
tDQSS MEM_DDR3_TDQSS_CYC tDQSS describes the skew between the memory clock (CK) and the output data strobes used for writes. It is the time between the rising data strobe edge (DQS, DQS#) relative to the rising CK edge.
tDSH MEM_DDR3_TDSH_CYC tDSH specifies the write DQS hold time. This is the time difference between the rising CK edge and the falling edge of DQS, measured as a percentage of tCK.
tDSS MEM_DDR3_TDSS_CYC tDSS describes the time between the falling edge of DQS to the rising edge of the next CK transition.
tDS (base) AC level MEM_DDR3_TDS_AC_MV tDS (base) AC level refers to the voltage level which the data bus must cross and remain above during the setup margin window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire setup period.
tDS (base) MEM_DDR3_TDS_PS tDS(base) refers to the setup time for the Data (DQ) bus before the rising edge of the DQS strobe.
tIH (base) DC level MEM_DDR3_TIH_DC_MV tIH (base) DC level refers to the voltage level which the address/command signal must not cross during the hold window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire hold period.
tIH (base) MEM_DDR3_TIH_PS tIH (base) refers to the hold time for the Address/Command (A) bus after the rising edge of CK. Depending on what AC level the user has chosen for a design, the hold margin can vary (this variance will be automatically determined when the user choses the "tIH (base) AC level").
tINIT MEM_DDR3_TINIT_US tINIT describes the time duration of the memory initialization after a device power-up. After RESET_n is de-asserted, wait for another 500us until CKE becomes active. During this time, the DRAM starts internal initialization; this happens independently of external clocks.
tIS (base) AC level MEM_DDR3_TIS_AC_MV tIS (base) AC level refers to the voltage level which the address/command signal must cross and remain above during the setup margin window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire setup period.
tIS (base) MEM_DDR3_TIS_PS tIS (base) refers to the setup time for the Address/Command/Control (A) bus to the rising edge of CK.
tMRD MEM_DDR3_TMRD_CK_CYC The mode register set command cycle time, tMRD is the minimum time period required between two MRS commands.
tQH MEM_DDR3_TQH_CYC tQH specifies the output hold time for the DQ in relation to DQS, DQS#. It is the length of time between the DQS, DQS# crossing to the earliest invalid transition of the fastest DQ pin in the DQ group associated with that DQS strobe.
tQSH MEM_DDR3_TQSH_CYC tQSH refers to the differential High Pulse Width, which is measured as a percentage of tCK. It is the time during which the DQS is high for a read.
tRAS MEM_DDR3_TRAS_NS tRAS describes the activate to precharge duration. A row cannot be deactivated until the tRAS time has been met. Therefore tRAS determines how long the memory has to wait after a activate command before a precharge command can be issued to close the row.
tRCD MEM_DDR3_TRCD_NS tRCD, row command delay, describes the amount of delay between the activation of a row through the RAS command and the access to the data through the CAS command.
tRP MEM_DDR3_TRP_NS tRP refers to the Precharge (PRE) command period. It describes how long it takes for the memory to disable access to a row by precharging and before it is ready to activate a different row.
tWLH MEM_DDR3_TWLH_PS tWLH describes the write leveling hold time from the rising edge of DQS to the rising edge of CK.
tWLS MEM_DDR3_TWLS_PS tWLS describes the write leveling setup time. It is measured from the rising edge of CK to the rising edge of DQS.
tWR MEM_DDR3_TWR_NS tWR refers to the Write Recovery time. It specifies the amount of clock cycles needed to complete a write before a precharge command can be issued.
Table 371.  Group: Mem Timing / Parameters dependent on Speed Bin, Operating Frequency, and Page Size
Display Name Identifier Description
tFAW MEM_DDR3_TFAW_NS tFAW refers to the four activate window time. It describes the period of time during which only four banks can be active.
tRRD MEM_DDR3_TRRD_CYC tRRD refers to the Row Active to Row Active Delay. It is the minimum time interval (measured in memory clock cycles) between two activate commands to rows in different banks in the same rank
tRTP MEM_DDR3_TRTP_CYC tRTP refers to the internal READ Command to PRECHARGE Command delay. It is the number of memory clock cycles that is needed between a read command and a precharge command to the same rank.
tWTR MEM_DDR3_TWTR_CYC tWTR or Write Timing Parameter describes the delay from start of internal write transaction to internal read command, for accesses to the same bank. The delay is measured from the first rising memory clock edge after the last write data is received to the rising memory clock edge when a read command is received.
Table 372.  Group: Mem Timing / Parameters dependent on Density and Temperature
Display Name Identifier Description
tREFI MEM_DDR3_TREFI_US tREFI refers to the average periodic refresh interval. It is the maximum amount of time the memory can tolerate in between each refresh command
tRFC MEM_DDR3_TRFC_NS tRFC refers to the Refresh Cycle Time. It is the amount of delay after a refresh command before an activate command can be accepted by the memory. This parameter is dependent on the memory density and is necessary for proper hardware functionality.
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message