External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

8.2.5. Simulating the Example Design

This topic describes how to simulate the example design in Cadence, Synopsys, Mentor Graphics, and Aldec simulators.

To simulate the example design in the Quartus Prime software using the Cadence simulator, follow these steps:

  1. At the Linux* shell command prompt, change directory to <name>_example_design\simulation\<verilog/vhdl>\cadence
  2. Run the simulation by typing the following command at the command prompt:
    sh ncsim_setup.sh

To simulate the example design in the Quartus Prime software using the Synopsys simulator, follow these steps:

  1. At the Linux* shell command prompt, change directory to <name>_example_design\simulation\<verilog/vhdl>\synopsys\vcsmx
  2. Run the simulation by typing the following command at the command prompt:
    sh vcsmx_setup.sh

To simulate the example design in the Quartus Prime software using the Mentor simulator, follow these steps:

  1. At the Linux* or Windows shell command prompt, change directory to <name>_example_design\simulation\<verilog/vhdl>\mentor
  2. Execute the msim_setup.tcl script that automatically compiles and runs the simulation by typing the following command at the Linux* or Windows command prompt:
    vsim -do run.do

    or

    Type the following command at the ModelSim* command prompt:

    do run.do
    

To simulate the example design in the Quartus Prime software using the Aldec simulator, follow these steps:

  1. At the Linux or Windows shell command prompt, change directory to <name>_example_design\simulation\<verilog/vhdl>\aldec
  2. Execute the rivierapro_setup.tcl script that automatically compiles and runs the simulation by typing the following command at the Linux or Windows command prompt:vsim -do rivierapro.tcl
  3. To compile and elaborate the design after the script loads, type ld_debug.
  4. Type run -all to run the simulation.

For more information about simulation, refer to the Simulating Designs chapter in volume 3 of the Quartus Prime Handbook.

If your Quartus Prime project appears to be configured correctly but the example testbench still fails, check the known issues on the Intel FPGA Knowledge Base before filing a service request.

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