External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.3.1.6. RLDRAM 3 UniPHY Interface

The following table lists the RLDRAM 3 signals available for each interface in Qsys and provides a description and guidance on how to connect those interfaces.
Table 61.  RLDRAM 3 UniPHY Interface

Signals in Interface

Interface Type

Description/How to Connect

pll_ref_clk interface

pll_ref_clk

Clock input

PLL reference clock input.

global_reset interface

global_reset_n

Reset input

Asynchronous global reset for PLL and all logic in PHY.

soft_reset interface

soft_reset_n

Reset input

Asynchronous reset input. Resets the PHY, but not the PLL that the PHY uses.

afi_reset interface

afi_reset_n

Reset output (PLL master/no sharing)

When the interface is in PLL master or no sharing modes, this interface is an asynchronous reset output of the AFI interface. The controller asserts this interface when the PLL loses lock or the PHY is reset.

afi_reset_export interface

afi_reset_export_n

Reset output (PLL master/no sharing)

This interface is a copy of the afi_reset interface. It is intended to be connected to PLL sharing slaves.

afi_reset_in interface

afi_reset_n

Reset input (PLL slave)

When the interface is in PLL slave mode, this interface is a reset input that you must connect to the afi_reset_export_n output of an identically configured memory interface in PLL master mode.

afi_clk interface

afi_clk

Clock output (PLL master/no sharing)

This AFI interface clock can be a full-rate or half-rate memory clock frequency based on the memory interface parameterization. When the interface is in PLL master or no sharing modes, this interface is a clock output.

afi_clk_in interface

afi_clk

Clock input (PLL slave)

This AFI interface clock can be a full-rate or half-rate memory clock frequency based on the memory interface parameterization. When the interface is in PLL slave mode, you must connect this afi_clk input to the afi_clk output of an identically configured memory interface in PLL master mode.

afi_half_clk interface

afi_half_clk

Clock output (PLL master/no sharing)

The AFI half clock that is half the frequency of afi_clk. When the interface is in PLL master or no sharing modes, this interface is a clock output.

afi_half_clk_in interface

afi_half_clk

Clock input (PLL slave)

The AFI half clock that is half the frequency of afi_clk. When the interface is in PLL slave mode, this is a clock input that you must connect to the afi_half_clk output of an identically configured memory interface in PLL master mode.

memory interface

mem_a

Conduit

Interface signals between the PHY and the memory device.

mem_ba

mem_ck

mem_ck_n

mem_cs_n

mem_dk

mem_dk_n

mem_dm

mem_dq

mem_qk

mem_qk_n

mem_ref_n

mem_we_n

mem_reset_n

afi interface

afi_addr

Avalon-MM Slave

Altera PHY interface (AFI) signals between the PHY and controller.

afi_ba

afi_cs_n

afi_we_n

afi_ref_n

afi_wdata_valid

afi_wdata

afi_dm

afi_rdata

afi_rdata_en

afi_rdata_en_full

afi_rdata_valid

afi_rst_n

afi_cal_success

afi_cal_fail

afi_wlat

afi_rlat

oct interface

oct_rzqin

Conduit

OCT reference resistor pins for rzqin.

pll_sharing interface

pll_mem_clk

Conduit

Interface signals for PLL sharing, to connect PLL masters to PLL slaves. This interface is enabled only when you set PLL sharing mode to master or slave.

pll_write_clk

pll_addr_cmd_clk

pll_locked

pll_avl_clk

pll_config_clk

pll_mem_phy_clk

afi_phy_clk

pll_write_clk_pre_phy_clk

pll_p2c_read_clk

pll_c2p_write_clk

dll_sharing interface

dll_delayctrl

Conduit

DLL sharing interface for connecting DLL masters to DLL slaves. This interface is enabled only when you set DLL sharing mode to master or slave.

dll_pll_locked

oct_sharing interface

seriesterminationcontrol

Conduit

OCT sharing interface for connecting OCT masters to OCT slaves. This interface is enabled only when you set OCT sharing mode to master or slave.

parallelterminationcontrol

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