External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

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ID 683385
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Planning Pin and FPGA Resources 2. DDR2 and DDR3 SDRAM Board Design Guidelines 3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines 4. LPDDR2 SDRAM Board Design Guidelines 5. RLDRAM II and RLDRAM 3 Board Design Guidelines 6. QDR II/II+ SRAM Board Design Guidelines 7. Implementing and Parameterizing Memory IP 8. Simulating Memory IP 9. Analyzing Timing of Memory IP 10. Debugging Memory IP 11. Optimizing the Controller 12. PHY Considerations 13. Power Estimation Methods for External Memory Interfaces
1. Planning Pin and FPGA Resources x
1.1. Interface Pins 1.2. Guidelines for UniPHY-based External Memory Interface IP 1.3. Using PLL Guidelines 1.4. PLL Cascading 1.5. DLL 1.6. Other FPGA Resources 1.7. Document Revision History
1.1. Interface Pins x
1.1.1. Estimating Pin Requirements 1.1.2. DDR, DDR2, and DDR3 SDRAM Clock Signals 1.1.3. DDR, DDR2, and DDR3 SDRAM Command and Address Signals 1.1.4. DDR, DDR2, and DDR3 SDRAM Data, Data Strobes, DM/DBI, and Optional ECC Signals 1.1.5. DDR, DDR2, and DDR3 SDRAM DIMM Options 1.1.6. QDR II and QDR II+ SRAM Clock Signals 1.1.7. QDR II and QDR II+ SRAM Command Signals 1.1.8. QDR II and QDR II+ SRAM Address Signals 1.1.9. QDR II and QDR II+ SRAM Data, BWS, and QVLD Signals 1.1.10. RLDRAM II and RLDRAM 3 Clock Signals 1.1.11. RLDRAM II and RLDRAM 3 Commands and Addresses 1.1.12. RLDRAM II and RLDRAM 3 Data, DM and QVLD Signals 1.1.13. LPDDR2 Clock Signal 1.1.14. LPDDR2 Command and Address Signal 1.1.15. LPDDR2 Data, Data Strobe, and DM Signals 1.1.16. Maximum Number of Interfaces 1.1.17. OCT Support
1.1.16. Maximum Number of Interfaces x
1.1.16.1. Maximum Number of DDR SDRAM Interfaces Supported per FPGA 1.1.16.2. Maximum Number of DDR2 SDRAM Interfaces Supported per FPGA 1.1.16.3. Maximum Number of DDR3 SDRAM Interfaces Supported per FPGA 1.1.16.4. Maximum Number of QDR II and QDR II+ SRAM Interfaces Supported per FPGA 1.1.16.5. Maximum Number of RLDRAM II Interfaces Supported per FPGA 1.1.16.6. Maximum Number of LPDDR2 SDRAM Interfaces Supported per FPGA
1.2. Guidelines for UniPHY-based External Memory Interface IP x
1.2.1. General Pin-out Guidelines for UniPHY-based External Memory Interface IP 1.2.2. Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II, Stratix III and Stratix IV Devices 1.2.3. Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces 1.2.4. Pin-out Rule Exceptions for QDR II and QDR II+ SRAM Burst-length-of-two Interfaces 1.2.5. Pin Connection Guidelines Tables 1.2.6. PLLs and Clock Networks
1.2.2. Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II, Stratix III and Stratix IV Devices x
1.2.2.1. Timing Impact on x36 Emulation 1.2.2.2. Rules to Combine Groups 1.2.2.3. Determining the CQ/CQn Arrival Time Skew
1.2.3. Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces x
1.2.3.1. Interfacing with ×9 RLDRAM II CIO Devices 1.2.3.2. Interfacing with ×18 RLDRAM II and RLDRAM 3 CIO Devices 1.2.3.3. Interfacing with RLDRAM II and RLDRAM 3 ×36 CIO Devices
1.2.5. Pin Connection Guidelines Tables x
1.2.5.1. DDR3 SDRAM With Leveling Interface Pin Utilization Applicable for Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices 1.2.5.2. QDR II and QDR II+ SRAM Pin Utilization for Arria II, Arria V, Stratix III, Stratix IV, and Stratix V Devices 1.2.5.3. RLDRAM II CIO Pin Utilization for Arria II GZ, Arria V, Stratix III, Stratix IV, and Stratix V Devices  1.2.5.4. LPDDR2 Pin Utilization for Arria V, Cyclone V, and MAX 10 FPGA Devices 1.2.5.5. Additional Guidelines for Arria V GZ and Stratix V Devices 1.2.5.6. Additional Guidelines for Arria V ( Except Arria V GZ) Devices 1.2.5.7. Additional Guidelines for MAX 10 Devices 1.2.5.8. Additional Guidelines for Cyclone V Devices
1.2.6. PLLs and Clock Networks x
1.2.6.1. Number of PLLs Available in Intel® Device Families 1.2.6.2. Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in Intel® Device Families 1.2.6.3. Number of Clock Networks Available in Intel® Device Families 1.2.6.4. Clock Network Usage in UniPHY-based Memory Interfaces—DDR2 and DDR3 SDRAM (1) (2) 1.2.6.5. Clock Network Usage in UniPHY-based Memory Interfaces—RLDRAM II, and QDR II and QDR II+ SRAM 1.2.6.6. PLL Usage for DDR, DDR2, and DDR3 SDRAM Without Leveling Interfaces 1.2.6.7. PLL Usage for DDR3 SDRAM With Leveling Interfaces
2. DDR2 and DDR3 SDRAM Board Design Guidelines x
2.1. Leveling and Dynamic Termination 2.2. DDR2 Terminations and Guidelines 2.3. DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V 2.4. Layout Approach 2.5. Channel Signal Integrity Measurement 2.6. Design Layout Guidelines 2.7. Package Deskew 2.8. Document Revision History
2.1. Leveling and Dynamic Termination x
2.1.1. Read and Write Leveling 2.1.2. Dynamic ODT 2.1.3. Dynamic On-Chip Termination 2.1.4. Dynamic On-Chip Termination in Stratix III and Stratix IV Devices 2.1.5. Dynamic OCT in Stratix V Devices
2.1.3. Dynamic On-Chip Termination x
2.1.3.1. FPGA Writing to Memory 2.1.3.2. FPGA Reading from Memory
2.2. DDR2 Terminations and Guidelines x
2.2.1. Termination for DDR2 SDRAM 2.2.2. DDR2 Design Layout Guidelines 2.2.3. General Layout Guidelines 2.2.4. Layout Guidelines for DDR2 SDRAM Interface
2.2.1. Termination for DDR2 SDRAM x
2.2.1.1. External Parallel Termination 2.2.1.2. On-Chip Termination 2.2.1.3. Recommended Termination Schemes
2.3. DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V x
2.3.1. Terminations for Single-Rank DDR3 SDRAM Unbuffered DIMM 2.3.2. Terminations for Multi-Rank DDR3 SDRAM Unbuffered DIMM 2.3.3. Terminations for DDR3 SDRAM Registered DIMM 2.3.4. Terminations for DDR3 SDRAM Load-Reduced DIMM 2.3.5. Terminations for DDR3 SDRAM Components With Leveling
2.3.5. Terminations for DDR3 SDRAM Components With Leveling x
2.3.5.1. DDR3 SDRAM Components With or Without Leveling
2.5. Channel Signal Integrity Measurement x
2.5.1. Importance of Accurate Channel Signal Integrity Information 2.5.2. Understanding Channel Signal Integrity Measurement 2.5.3. How to Enter Calculated Channel Signal Integrity Values 2.5.4. Guidelines for Calculating DDR3 Channel Signal Integrity
2.6. Design Layout Guidelines x
2.6.1. General Layout Guidelines 2.6.2. Layout Guidelines for DDR3 SDRAM Interfaces 2.6.3. Length Matching Rules 2.6.4. Spacing Guidelines 2.6.5. Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits)
2.6.5. Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits) x
2.6.5.1. Fly-By Network Design for Clock, Command, and Address Signals
2.7. Package Deskew x
2.7.1. Package Deskew Recommendation for Stratix V Devices 2.7.2. DQ/DQS/DM Deskew 2.7.3. Address and Command Deskew 2.7.4. Deskew Example 2.7.5. Package Migration 2.7.6. Package Deskew for RLDRAM II and RLDRAM 3
3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines x
3.1. General Layout Guidelines 3.2. Dual-Slot Unbuffered DDR2 SDRAM 3.3. Dual-Slot Unbuffered DDR3 SDRAM 3.4. Document Revision History
3.2. Dual-Slot Unbuffered DDR2 SDRAM x
3.2.1. Overview of ODT Control 3.2.2. DIMM Configuration 3.2.3. Dual-DIMM Memory Interface with Slot 1 Populated 3.2.4. Dual-DIMM with Slot 2 Populated 3.2.5. Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated 3.2.6. Dual-DIMM DDR2 Clock, Address, and Command Termination and Topology 3.2.7. Control Group Signals 3.2.8. Clock Group Signals
3.2.3. Dual-DIMM Memory Interface with Slot 1 Populated x
3.2.3.1. FPGA Writing to Memory 3.2.3.2. Write to Memory Using an ODT Setting of 150-ohm 3.2.3.3. Reading from Memory
3.2.4. Dual-DIMM with Slot 2 Populated x
3.2.4.1. FPGA Writing to Memory 3.2.4.2. Write to Memory Using an ODT Setting of 150-ohm 3.2.4.3. Reading from Memory
3.2.5. Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated x
3.2.5.1. FPGA Writing to Memory 3.2.5.2. Write to Memory in Slot 1 Using an ODT Setting of 75-ohm 3.2.5.3. Reading From Memory
3.3. Dual-Slot Unbuffered DDR3 SDRAM x
3.3.1. Comparison of DDR3 and DDR2 DQ and DQS ODT Features and Topology 3.3.2. Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology 3.3.3. FPGA OCT Features
3.3.2. Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology x
3.3.2.1. Address and Command Signals 3.3.2.2. Control Group Signals 3.3.2.3. Clock Group Signals
3.3.3. FPGA OCT Features x
3.3.3.1. Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V Devices 3.3.3.2. Arria II GX Devices
4. LPDDR2 SDRAM Board Design Guidelines x
4.1. LPDDR2 Guidance 4.2. Document Revision History
4.1. LPDDR2 Guidance x
4.1.1. LPDDR2 SDRAM Configurations 4.1.2. OCT Signal Terminations for Arria V and Cyclone V Devices 4.1.3. General Layout Guidelines 4.1.4. LPDDR2 Layout Guidelines
4.1.2. OCT Signal Terminations for Arria V and Cyclone V Devices x
4.1.2.1. Outputs from the FPGA to the LPDDR2 Component 4.1.2.2. Input to the FPGA from the LPDDR2 SDRAM Component 4.1.2.3. Termination Schemes
5. RLDRAM II and RLDRAM 3 Board Design Guidelines x
5.1. RLDRAM II Configurations 5.2. RLDRAM 3 Configurations 5.3. Signal Terminations 5.4. PCB Layout Guidelines 5.5. General Layout Guidelines 5.6. RLDRAM II and RLDRAM 3 Layout Guidelines 5.7. Layout Approach 5.8. Package Deskew for RLDRAM II and RLDRAM 3 5.9. Document Revision History
5.3. Signal Terminations x
5.3.1. Input to the FPGA from the RLDRAM Components 5.3.2. Outputs from the FPGA to the RLDRAM II and RLDRAM 3 Components 5.3.3. RLDRAM II Termination Schemes 5.3.4. RLDRAM 3 Termination Schemes
5.7. Layout Approach x
5.7.1. Arria V and Stratix V Board Setting Parameters
6. QDR II/II+ SRAM Board Design Guidelines x
6.1. QDR II SRAM Configurations 6.2. Signal Terminations 6.3. General Layout Guidelines 6.4. QDR II Layout Guidelines 6.5. QDR II SRAM Layout Approach 6.6. Package Deskew for QDR II 6.7. Document Revision History
6.2. Signal Terminations x
6.2.1. Output from the FPGA to the QDR II SRAM Component 6.2.2. Input to the FPGA from the QDR II SRAM Component 6.2.3. Termination Schemes
7. Implementing and Parameterizing Memory IP x
7.1. Design Flow 7.2. UniPHY-Based External Memory Interface IP 7.3. Document Revision History
7.1. Design Flow x
7.1.1. IP Catalog Design Flow 7.1.2. Platform Designer System Integration Tool Design Flow
7.1.1. IP Catalog Design Flow x
7.1.1.1. IP Catalog and Parameter Editor 7.1.1.2. Specifying Parameters for the IP Catalog Flow 7.1.1.3. Using Example Designs 7.1.1.4. Constraining the Design 7.1.1.5. Compiling the Design
7.1.1.4. Constraining the Design x
7.1.1.4.1. Adding Pins and DQ Group Assignments
7.1.2. Platform Designer System Integration Tool Design Flow x
7.1.2.1. Specify Parameters for the Platform Designer Flow 7.1.2.2. Completing the Platform Designer System
7.2. UniPHY-Based External Memory Interface IP x
7.2.1. Platform Designer Interfaces 7.2.2. Generated Files for Memory Controllers with the UniPHY IP 7.2.3. Parameterizing Memory Controllers 7.2.4. Board Settings 7.2.5. Controller Settings for UniPHY IP 7.2.6. Diagnostics for UniPHY IP
7.2.1. Platform Designer Interfaces x
7.2.1.1. DDR2 SDRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.2. DDR3 SDRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.3. LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.4. QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.5. RLDRAM II Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.6. RLDRAM 3 UniPHY Intel FPGA IP Interface
7.2.3. Parameterizing Memory Controllers x
7.2.3.1. PHY Settings for UniPHY IP 7.2.3.2. Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM Controller with UniPHY Intel FPGA IP 7.2.3.3. Memory Parameters for QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP 7.2.3.4. Memory Parameters for RLDRAM II Controller with UniPHY Intel FPGA IP 7.2.3.5. Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP 7.2.3.6. Memory Timing Parameters for QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP 7.2.3.7. Memory Timing Parameters for RLDRAM II Controller with UniPHY Intel FPGA IP 7.2.3.8. Memory Parameters for RLDRAM 3 UniPHY Intel FPGA IP
7.2.3.2. Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM Controller with UniPHY Intel FPGA IP x
7.2.3.2.1. Memory Initialization Options for DDR2 7.2.3.2.2. Memory Initialization Options for DDR3 7.2.3.2.3. Memory Initialization Options for LPDDR2
7.2.4. Board Settings x
7.2.4.1. Setup and Hold Derating for UniPHY IP 7.2.4.2. Intersymbol Interference Channel Signal Integrity for UniPHY IP 7.2.4.3. Board Skews for UniPHY IP
7.2.4.3. Board Skews for UniPHY IP x
7.2.4.3.1. Board Skew Parameters for LPDDR2/DDR2/DDR3 SDRAM 7.2.4.3.2. Board Skew Parameters for QDR II and QDR II+ 7.2.4.3.3. Board Skew parameters for RLDRAM II and RLDRAM 3
8. Simulating Memory IP x
8.1. Simulation Options 8.2. Simulation Walkthrough with UniPHY IP 8.3. Document Revision History
8.2. Simulation Walkthrough with UniPHY IP x
8.2.1. Simulation Scripts 8.2.2. Preparing the Vendor Memory Model 8.2.3. Functional Simulation with Verilog HDL 8.2.4. Functional Simulation with VHDL 8.2.5. Simulating the Example Design 8.2.6. UniPHY Abstract PHY Simulation 8.2.7. PHY-Only Simulation 8.2.8. Post-fit Functional Simulation 8.2.9. Simulation Issues
8.2.8. Post-fit Functional Simulation x
8.2.8.1. Running Post-fit Simulation
9. Analyzing Timing of Memory IP x
9.1. Memory Interface Timing Components 9.2. FPGA Timing Paths 9.3. Timing Constraint and Report Files for UniPHY IP 9.4. Timing Analysis Description 9.5. Timing Report DDR 9.6. Report SDC 9.7. Calibration Effect in Timing Analysis 9.8. Timing Model Assumptions and Design Rules 9.9. Common Timing Closure Issues 9.10. Optimizing Timing 9.11. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs 9.12. Performing I/O Timing Analysis 9.13. Document Revision History
9.1. Memory Interface Timing Components x
9.1.1. Source-Synchronous Paths 9.1.2. Calibrated Paths 9.1.3. Internal FPGA Timing Paths 9.1.4. Other FPGA Timing Parameters
9.2. FPGA Timing Paths x
9.2.1. Arria II Device PHY Timing Paths 9.2.2. Stratix III and Stratix IV PHY Timing Paths 9.2.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Timing paths
9.4. Timing Analysis Description x
9.4.1. UniPHY IP Timing Analysis
9.4.1. UniPHY IP Timing Analysis x
9.4.1.1. Address and Command 9.4.1.2. PHY or Core 9.4.1.3. PHY or Core Reset 9.4.1.4. Read Capture and Write 9.4.1.5. Read Resynchronization 9.4.1.6. DQS versus CK—Arria II GX and Cyclone IV Devices 9.4.1.7. Write Leveling tDQSS 9.4.1.8. Write Leveling tDSH/tDSS 9.4.1.9. DK versus CK (RLDRAM II with UniPHY) 9.4.1.10. Bus Turnaround Time
9.4.1.4. Read Capture and Write x
9.4.1.4.1. Stratix III 9.4.1.4.2. Arria II, Arria V, Cyclone V, Stratix IV and Stratix V
9.7. Calibration Effect in Timing Analysis x
9.7.1. Calibration Emulation for Calibrated Path 9.7.2. Calibration Error or Quantization Error 9.7.3. Calibration Uncertainties 9.7.4. Memory Calibration
9.8. Timing Model Assumptions and Design Rules x
9.8.1. Memory Clock Output Assumptions 9.8.2. Write Data Assumptions 9.8.3. Read Data Assumptions 9.8.4. DLL Assumptions 9.8.5. PLL and Clock Network Assumptions for Stratix III Devices
9.8.1. Memory Clock Output Assumptions x
9.8.1.1. Memory Clock Assumptions for Stratix III Devices
9.8.2. Write Data Assumptions x
9.8.2.1. Write Data Assumptions for Stratix III Devices
9.8.3. Read Data Assumptions x
9.8.3.1. Read Data Assumptions for Stratix III Devices
9.9. Common Timing Closure Issues x
9.9.1. Missing Timing Margin Report 9.9.2. Incomplete Timing Margin Report 9.9.3. Read Capture Timing 9.9.4. Write Timing 9.9.5. Address and Command Timing 9.9.6. PHY Reset Recovery and Removal 9.9.7. Clock-to-Strobe (for DDR and DDR2 SDRAM Only) 9.9.8. Read Resynchronization and Write Leveling Timing (for SDRAM Only)
9.11. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs x
9.11.1. Multiple Chip Select Configuration Effects 9.11.2. Timing Deration using the Board Settings
9.11.1. Multiple Chip Select Configuration Effects x
9.11.1.1. ISI Effects 9.11.1.2. Calibration Effects 9.11.1.3. Board Effects
9.11.2. Timing Deration using the Board Settings x
9.11.2.1. Slew Rates 9.11.2.2. Slew Rate Setup, Hold, and Derating Calculation 9.11.2.3. Intersymbol Interference 9.11.2.4. Measuring Eye Reduction for Address/Command, DQ, and DQS Setup and Hold Time
9.12. Performing I/O Timing Analysis x
9.12.1. Performing I/O Timing Analysis with Third-Party Simulation Tools 9.12.2. Performing Advanced I/O Timing Analysis with Board Trace Delay Model
10. Debugging Memory IP x
10.1. Resource and Planning Issues 10.2. Interface Configuration Performance Issues 10.3. Functional Issue Evaluation 10.4. Timing Issue Characteristics 10.5. Verifying Memory IP Using the Signal Tap II Logic Analyzer 10.6. Hardware Debugging Guidelines 10.7. Categorizing Hardware Issues 10.8. EMIF Debug Toolkit Overview 10.9. Document Revision History
10.1. Resource and Planning Issues x
10.1.1. Dedicated DLL Resources 10.1.2. Dedicated IOE DQS Group Resources and Pins 10.1.3. Specific PLL Resources 10.1.4. Specific Global, Regional and Dual-Regional Clock Net Resources 10.1.5. Planning Your Design 10.1.6. Optimizing Design Utilization
10.2. Interface Configuration Performance Issues x
10.2.1. Interface Configuration Bottleneck and Efficiency Issues
10.3. Functional Issue Evaluation x
10.3.1. Correct Combination of the Quartus Prime Software and ModelSim* - Intel® FPGA Edition Device Models 10.3.2. Intel® IP Memory Model 10.3.3. Vendor Memory Model 10.3.4. Insufficient Memory in Your PC 10.3.5. Transcript Window Messages 10.3.6. Passing Simulation 10.3.7. Modifying the Example Driver to Replicate the Failure
10.4. Timing Issue Characteristics x
10.4.1. Evaluating FPGA Timing Issues 10.4.2. Evaluating External Memory Interface Timing Issues
10.5. Verifying Memory IP Using the Signal Tap II Logic Analyzer x
10.5.1. Signals to Monitor with the Signal Tap II Logic Analyzer
10.6. Hardware Debugging Guidelines x
10.6.1. Create a Simplified Design that Demonstrates the Same Issue 10.6.2. Measure Power Distribution Network 10.6.3. Measure Signal Integrity and Setup and Hold Margin 10.6.4. Vary Voltage 10.6.5. Use Freezer Spray and Heat Gun 10.6.6. Operate at a Lower Speed 10.6.7. Determine Whether the Issue Exists in Previous Versions of Software 10.6.8. Determine Whether the Issue Exists in the Current Version of Software 10.6.9. Try A Different PCB 10.6.10. Try Other Configurations 10.6.11. Debugging Checklist
10.7. Categorizing Hardware Issues x
10.7.1. Signal Integrity Issues 10.7.2. Hardware and Calibration Issues
10.7.1. Signal Integrity Issues x
10.7.1.1. Characteristics of Signal Integrity Issues 10.7.1.2. Evaluating SignaI Integrity Issues
10.7.1.2. Evaluating SignaI Integrity Issues x
10.7.1.2.1. Skew 10.7.1.2.2. Crosstalk 10.7.1.2.3. Power System 10.7.1.2.4. Clock Signals 10.7.1.2.5. Read Data Valid Window and Eye Diagram 10.7.1.2.6. Write Data Valid Window and Eye Diagram 10.7.1.2.7. OCT and ODT Usage
10.7.2. Hardware and Calibration Issues x
10.7.2.1. Evaluating Hardware and Calibration Issues
10.7.2.1. Evaluating Hardware and Calibration Issues x
10.7.2.1.1. Write Timing Margin 10.7.2.1.2. Read Timing Margin 10.7.2.1.3. Address and Command Timing Margin 10.7.2.1.4. Resynchronization Timing Margin 10.7.2.1.5. Postamble Timing Issues and Margin 10.7.2.1.6. Intermittent Issue Evaluation
11. Optimizing the Controller x
11.1. Factors Affecting Efficiency 11.2. Ways to Improve Efficiency 11.3. Document Revision History
11.1. Factors Affecting Efficiency x
11.1.1. Interface Standard 11.1.2. Bank Management Efficiency 11.1.3. Data Transfer
11.2. Ways to Improve Efficiency x
11.2.1. DDR2 SDRAM Controller 11.2.2. Auto-Precharge Commands 11.2.3. Additive Latency 11.2.4. Bank Interleaving 11.2.5. Command Queue Look-Ahead Depth 11.2.6. Additive Latency and Bank Interleaving 11.2.7. User-Controlled Refresh 11.2.8. Frequency of Operation 11.2.9. Burst Length 11.2.10. Series of Reads or Writes 11.2.11. Data Reordering 11.2.12. Starvation Control 11.2.13. Command Reordering 11.2.14. Bandwidth 11.2.15. Efficiency Monitor
12. PHY Considerations x
12.1. Core Logic and User Interface Data Rate 12.2. Hard and Soft Memory PHY 12.3. Sequencer 12.4. PLL, DLL and OCT Resource Sharing 12.5. Pin Placement Consideration 12.6. Document Revision History
13. Power Estimation Methods for External Memory Interfaces x
13.1. Performing Vector-Based Power Analysis with the Power Analyzer 13.2. Document Revision History
1. Planning Pin and FPGA Resources
2. DDR2 and DDR3 SDRAM Board Design Guidelines
3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines
4. LPDDR2 SDRAM Board Design Guidelines
5. RLDRAM II and RLDRAM 3 Board Design Guidelines
6. QDR II/II+ SRAM Board Design Guidelines
7. Implementing and Parameterizing Memory IP
8. Simulating Memory IP
9. Analyzing Timing of Memory IP
10. Debugging Memory IP
11. Optimizing the Controller
12. PHY Considerations
13. Power Estimation Methods for External Memory Interfaces

7.4.1. Qsys Interfaces

The interfaces in the Arria® 10 External Memory Interface IP each have signals that can be connected in Qsys. The following tables list the signals available for each interface and provide a description and guidance on how to connect those interfaces.

Listed interfaces and signals are available in all configurations unless stated otherwise in the description column. For Arria® 10 External Memory Interface for HPS, the global_reset_reset_sink, pll_ref_clk_clock_sink, hps_emif_conduit_end, oct_conduit_end and mem_conduit_end interfaces are the only available interfaces regardless of your configuration.

Arria® 10 External Memory Interface IP Interfaces

Table 85.  Interface: afi_clk_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
afi_clk Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3, QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) clock output signal. The clock frequency in relation to the memory clock frequency depends on the Clock rate of user logic value set in the parameter editor.

Connect this interface to the (clock input) conduit of the custom AFI-based memory controller connected to the afi_conduit_end or any user logic block that requires the generated clock frequency.

Table 86.  Interface: afi_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
afi_cal_success Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3, QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) signals between the external memory interface IP and the custom AFI-based memory controller.

Connect this interface to the AFI conduit of the custom AFI-based memory controller.

afi_cal_fail Output
afi_cal_req Input
afi_rlat Output
afi_wlat Output
afi_addr Input
afi_rst_n Input
afi_wdata_valid Input
afi_wdata Input
afi_rdata_en_full Input
afi_rdata Output
afi_rdata_valid Output
afi_rrank Input
afi_wrank Input
afi_ba Input
  • DDR3, DDR4, RLDRAM 3
  • Hard PHY only
afi_cs_n Input
  • DDR3, DDR4, LPDDR3, RLDRAM 3
  • Hard PHY only
afi_cke Input
  • DDR3, DDR4, LPDDR3
  • Hard PHY only
afi_odt Input
afi_dqs_burst Input
afi_ap Input
  • QDR IV
  • Hard PHY only
afi_pe_n Output
afi_ainv Input
afi_ld_n Input
afi_rw_n Input
afi_cfg_n Input
afi_lbk0_n Input
afi_lbk1_n Input
afi_rdata_dinv Output
  • QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) signals between the external memory interface IP and the custom AFI-based memory controller.

Connect this interface to the AFI conduit of the custom AFI-based memory controller.

afi_wdata_dinv Input
afi_we_n Input
  • DDR3, RLDRAM 3
  • Hard PHY only
The Altera PHY Interface (AFI) signals between the external memory interface IP and the custom AFI-based memory controller.

Connect this interface to the AFI conduit of the custom AFI-based memory controller.

For more information, refer to the AFI 4.0 Specification.

afi_dm Input
  • DDR3, LPDDR3, RLDRAM 3
  • Hard PHY only
  • Enable DM pins=True
afi_ras_n Input
  • DDR3
  • Hard PHY only
afi_cas_n Input
afi_rm Input
  • DDR3
  • Hard PHY only
  • LRDIMM with Number of rank multiplication pins > 0
afi_par Input
  • DDR3
  • Hard PHY only
  • RDIMM/LRDIMM
  • DDR4
  • Hard PHY only
  • Enable alert_n/par pins = True
afi_bg Input
  • DDR4
  • Hard PHY only
afi_act_n Input
afi_dm_n Input
  • DDR4
  • Hard PHY only
  • Enable DM pins=True
afi_ref_n Input
  • RLDRAM 3
  • Hard PHY only
Table 87.  Interface: afi_half_clk_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
afi_half_clk Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3, QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) half clock output signal. The clock runs at half the frequency of the AFI clock (afi_clk clock).

Connect this interface to the clock input conduit of the user logic block that needs to be clocked at the generated clock frequency.

Table 88.  Interface: afi_reset_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
afi_reset_n Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3, QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) reset output signal. Asserted when the PLL becomes unlocked or when the PHY is reset. Asynchronous assertion and synchronous deassertion.

Connect this interface to the reset input conduit of the custom AFI-based memory controller connected to the afi_conduit_end and all the user logic blocks that are under the AFI clock domain afi_clk or afi_half_clk clock).

Table 89.  Interface: cal_debug_avalon_slaveInterface type: Avalon Memory-Mapped Slave
Signals in Interface Direction Availability Description
cal_debug_waitrequest Output
  • EMIF Debug Toolkit
  • On-Chip Debug Port=Export
The Avalon-MM signals between the external memory interface IP and the external memory interface Debug Component.

Connect this interface to the (to_ioaux) Avalon-MM master of the Arria 10 EMIF Debug Component IP or to (cal_debug_out_avalon_master) Avalon-MM master of the other external memory interface IP that has exported the interface. If you are not using the Altera EMIF Debug Toolkit, connect this interface to the Avalon-MM master of the custom debug logic.

When in daisy-chaining mode, ensure one of the connected Avalon masters is either the Arria 10 EMIF Debug Component IP or the external memory interface IP with EMIF Debug Toolkit/On-Chip Debug Port set to Add EMIF Debug Interface.

cal_debug_read Input
cal_debug_write Input
cal_debug_addr Input
cal_debug_read_data Output
cal_debug_write_data Input
cal_debug_byteenable Input
cal_debug_read_data_valid Output
Table 90.  Interface: cal_debug_clk_clock_sinkInterface type: Clock Input
Signals in Interface Direction Availability Description
cal_debug_clk Input
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
The calibration debug clock input signal.

Connect this interface to the (avl_clk_out) clock output of the Arria 10 EMIF Debug Component IP or to (cal_debug_out_clk_clock_source) clock input of the other external memory interface IP, depending on which IP the cal_debug_avalon_slave interface is connecting to. If you are not using the Altera EMIF Debug Toolkit, connect this interface to the clock output of the custom debug logic.

Table 91.  Interface: cal_debug_out_avalon_masterInterface type: Avalon Memory-Mapped Master
Signals in Interface Direction Availability Description
cal_debug_out_waitrequest Input
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
  • Add EMIF Debug Interface with Enable Daisy-Chaining for EMIF Debug Toolkit/ On-Chip Debug Port=True
The Avalon-MM signals between the external memory interface IP and the other external memory interface IP.

Connect this interface to the (cal_debug_avalon_slave) Avalon-MM Master of the external memory interface IP that has exported the interface .

cal_debug_out_read Output
cal_debug_out_write Output
cal_debug_out_addr Output
cal_debug_out_read_data Input
cal_debug_out_write_data Output
   
cal_debug_out_byteenable Output
cal_debug_out_read_data_valid Input
Table 92.  Interface: cal_debug_out_clk_clock_sourceInterface type: Clock Output
Signals in Interface Direction Availability Description
cal_debug_out_clk Output
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
  • Add EMIF Debug Interface with Enable Daisy-Chaining for EMIF Debug Toolkit/ On-Chip Debug Port=True
The calibration debug clock output signal.

For EMIF Debug Toolkit/On-Chip Debug Port=Export with Enable Daisy-Chaining for EMIF Debug Toolkit/ On-Chip Debug Port=True, the clock frequency follows the cal_debug_clk frequency. Otherwise, the clock frequency in relation to the memory clock frequency depends on the Clock rate of user logic value set in the parameter editor.

Connect this interface to the (cal_debug_out_reset_reset_source) clock input of the other external memory interface IP where the cal_debug_avalon_master interface is being connected to or to any user logic block that needs to be clocked at the generated clock frequency.

Table 93.  Interface: cal_debug_out_reset_reset_sourceInterface type: Reset Output
Signals in Interface Direction Availability Description
cal_debug_out_reset_n Output
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
  • Add EMIF Debug Interface with Enable Daisy-Chaining for EMIF Debug Toolkit/ On-Chip Debug Port=True
The calibration debug reset output signal. Asynchronous assertion and synchronous deassertion.

Connect this interface to the (cal_debug_reset_reset_sink) reset input of the other external memory interface IP where the cal_debug_avalon_master interface being connected to and all the user logic blocks that are under the calibration debug clock domain (cal_debug_out_clk clock reset). If you are not using the Altera EMIF Debug Toolkit, connect this interface to the reset output of the custom debug logic.

Table 94.  Interface: cal_debug_reset_reset_sinkInterface type: Reset Intput
Signals in Interface Direction Availability Description
cal_debug_reset_n Input
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
The calibration debug reset input signal. Require asynchronous assertion and synchronous deassertion.

Connect this interface to the (avl_rst_out) reset output of the Arria 10 EMIF Debug Component IP or to (cal_debug_out_reset_reset_source) clock input of the other external memory interface IP, depending on which IP the cal_debug_avalon_slave interface is being connected to.

Table 95.  Interface: clks_sharing_master_out_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
clks_sharing_master_out Input
  • Core clocks sharing=Master
The core clock output signals.

Connect this interface to the (clks_sharing_slave_in_conduit_end) conduit of the other external memory interface IP with the Core clock sharing set to slave or other PLL Slave.

Table 96.  Interface: clks_sharing_slave_in_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
clks_sharing_slave_in Input
  • Core clocks sharing=Slave
The core clock input signals.

Connect this interface to the (clks_sharing_master_out_conduit_end) conduit of the other external memory interface IP with the Core clock sharing set to Master or other PLL Master.

Table 97.  Interface: ctrl_amm_avalon_slaveInterface type: Avalon Memory-Mapped Slave
Signals in Interface Direction Availability Description
amm_ready Output
  • DDR3, DDR4 with Hard PHY & Hard Controller
  • QDR II/II+/II+ Xtreme, QDR IV
The Avalon-MM signals between the external memory interface IP and the user logic.

Connect this interface to the Avalon-MM Master of the user logic that needs to access the external memory device. For QDR II/II+/II+ Xtreme, connect the ctrl_amm_avalon_slave_0 to the user logic for read request and connect the ctrl_amm_avalon_slave_1 to the user logic for write request.

In Ping Pong PHY mode, each interface controls only one memory device. Connect ctrl_amm_avalon_slave_0 to the user logic that will access the first memory device, and connect ctrl_amm_avalon_slave_1 to the user logic that will access the secondary memory device.

amm_read Input
amm_write Input
amm_address Input
amm_readdata Output
amm_writedata Input
amm_burstcount Input
amm_readdatavalid Output
amm_byteenable Input
  • DDR3, DDR4 with Hard PHY & Hard Controller and Enable DM pins=True
  • QDR II/II+/II+ Xtreme with Enable BWS# pins=True
Table 98.  Interface: ctrl_auto_precharge_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
ctrl_auto_precharge_req Input
  • DDR3, DDR4 with Hard PHY & Hard Controller and Enable Auto-Precharge Control=True
The auto-precharge control input signal. Asserting the ctrl_auto_precharge_req signal while issuing a read or write burst instructs the external memory interface IP to issue read or write with auto-precharge to the external memory device. This precharges the row immediately after the command currently accessing it finishes, potentially speeding up a future access to a different row of the same bank.

Connect this interface to the conduit of the user logic block that controls when the external memory interface IP needs to issue read or write with auto-precharge to the external memory device.

Table 99.  Interface: ctrl_ecc_user_interrupt_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
ctrl_ecc_user_interrupt Output
  • DDR3, DDR4 with Hard PHY & Hard Controller and Enable Error Detection and Correction Logic = True

Controller ECC user interrupt interface for connection to a custom control block that must be notified when ECC errors occur.

Table 100.  Interface: ctrl_mmr_avalon_slaveInterface type: Avalon Memory-Mapped Slave
Signals in Interface Direction Availability Description
mmr_waitrequest Output
  • DDR3, DDR4, LPDDR3 with Hard PHY & Hard Controller and Enable Memory-Mapped Configuration and Status Register (MMR)=True

The Avalon-MM signals between the external memory interface IP and the user logic.

Connect this interface to the Avalon-MM master of the user logic that needs to access the Memory-Mapped Configuration and Status Register (MMR) in the external memory interface IP.

mmr_read Input
mmr_write Input
mmr_address Input
mmr_readdata Output
mmr_writedata Input
mmr_burstcount Input
mmr_byteenable Input
mmr_beginbursttransfer Input
mmr_readdatavalid Output
Table 101.  Interface: ctrl_power_down_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
ctrl_power_down_ack Output
  • DDR3, DDR4, LPDDR3 with Hard PHY & Hard Controller and Enable Auto Power Down=True
The auto power-down acknowledgment signals. When the ctrl_power_down_ack signal is asserted, it indicates that the external memory interface IP is placing the external memory device into power-down mode.

Connect this interface to the conduit of the user logic block that requires the auto power-down status, or leave it unconnected.

Table 102.  Interface: ctrl_user_priority_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
ctrl_user_priority_hi Input
  • DDR3, DDR4, LPDDR3 with Hard PHY & Hard Controller
  • Avalon Memory-Mapped and Enable Command Priority Control=true
The command priority control input signal. Asserting the ctrl_user_priority_hi signal while issuing a read or write request instructs the external memory interface to treat it as a high-priority command. The external memory interface attempts to execute high-priority commands sooner, to reduce latency.

Connect this interface to the conduit of the user logic block that determines when the external memory interface IP treats the read or write request as a high-priority command.

Table 103.  Interface: emif_usr_clk_clock_sourceInterface type: Clock Output
Signals in Interface Direction Availability Description
emif_usr_clk Output
  • DDR3, DDR4, LPDDR3, with Hard PHY & Hard Controller
  • QDR II/II+/II+ Xtreme
  • QDR IV
The user clock output signal. The clock frequency in relation to the memory clock frequency depends on the Clock rate of user logic value set in the parameter editor.

Connect this interface to the clock input of the respective user logic connected to the ctrl_amm_avalon_slave_0 interface, or to any user logic block that must be clocked at the generated clock frequency.

Table 104.  Interface: emif_usr_reset_reset_sourceInterface type: Reset Output
Signals in Interface Direction Availability Description
emif_usr_reset_n Output
  • DDR3, DDR4, LPDDR3 with Hard PHY & Hard Controller
  • QDR II/II+/II+ Xtreme
  • QDR IV
The user reset output signal. Asserted when the PLL becomes unlocked or the PHY is reset. Asynchronous assertion and synchronous deassertion.

Connect this interface to the clock input of the respective user logic connected to the ctrl_amm_avalon_slave_0 interface, or to any user logic block that must be clocked at the generated clock frequency.

Table 105.  Interface: emif_usr_clk_sec_clock_sourceInterface type: Clock Output
Signals in Interface Direction Availability Description
emif_usr_clk_sec Output
  • DDR3, DDR4, with Ping Pong PHY
 The user clock output signal. The clock frequency in relation to the memory clock frequency depends on the Clock rate of user logic value set in the parameter editor.

Connect this interface to the clock input of the respective user logic connected to the ctrl_amm_avalon_slave_1 interface, or to any user logic block that must be clocked at the generated clock frequency.

Table 106.  Interface: emif_usr_reset_sec_reset_sourceInterface type: Reset Output
Signals in Interface Direction Availability Description
emif_usr_reset_n_sec Output
  • DDR3, DDR4, with Ping Pong PHY
 The user reset output signal. Asserted when the PLL becomes unlocked or the PHY is reset. Asynchronous assertion and synchronous deassertion.

Connect this interface to the clock input of the respective user logic connected to the ctrl_amm_avalon_slave_1 interface, or to any user logic block that must be clocked at the generated clock frequency.

Table 107.  Interface: global_reset_reset_sinkInterface type: Reset Input
Signals in Interface Direction Availability Description
global_reset_n Input
  • Core Clock Sharing=No Sharing / Master
The global reset input signal. Asserting the global_reset_n signal causes the external memory interface IP to be reset and recalibrated.

Connect this interface to the reset output of the asynchronous or synchronous reset source that controls when the external memory interface IP needs to be reset and recalibrated.

Table 108.  Interface: hps_emif_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
hps_to_emif Input
  • Arria 10 EMIF for HPS IP
The user interface signals between the external memory interface IP and the Hard Processor System (HPS).

Connect this interface to the EMIF conduit of the Arria 10 Hard Processor System.

emif_to_hps Output
Table 109.  Interface: mem_conduit_endInterface type: Conduit

The memory interface signals between the external memory interface IP and the external memory device.

Export this interface to the top level for I/O assignments. Typically mem_rm[0] and mem_rm[1] connect to CS2# and CS3# of the memory buffer of all LRDIMM slots.

Signals in Interface Direction Availability
mem_ck Output Always available
mem_ck_n Output
mem_reset_n Output
mem_a Output
mem_k_n Output
  • QDR II
mem_ras_n Output
  • DDR3
mem_cas_n Output
mem_odt Output
  • DDR3, DDR4, LPDDR3
mem_dqs Bidirectional
mem_dqs_n Bidirectional
mem_ba Output
  • DDR3, DDR4, RLDRAM 3
mem_cs_n Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3
mem_dq Bidirectional
mem_we_n Output
  • DDR3, RLDRAM 3
mem_dm Output
  • DDR3, LPDDR3, RLDRAM 3 with Enable DM pins=True
mem_rm Output
  • DDR3, RLDRAM 3 with Memory format=LRDIMM and Number of rank multiplication pins > 0
mem_par Output
  • DDR3 with Memory format=RDIMM / LRDIMM
  • DDR4 with Enable alert_n/par pins=True
mem_alert_n Input
mem_cke Output
  • DDR3, DDR4, LPDDR3
mem_bg Output
  • DDR4
mem_act_n Output
mem_dbi_n Bidirectional
  • DDR4 with Enable DM pins=True or Write DBI=True or Read DBI=True
mem_k Output
  • QDR II/II+/II+ Xtreme
mem_wps_n Output
mem_rps_n Output
mem_doff_n Output
mem_d Output
mem_q Input
mem_cq Input
mem_cq_n Input
mem_bws_n Output
mem_dk Output
mem_dk_n Output
mem_ref_n Output
mem_qk Input
  • QDR II/II+/II+ Xtreme with Enable BWS# pins=True
mem_qk_n Input
  • RLDRAM 3
mem_ap Output
  • QDR IV with Use Address Parity Bit=True
mem_pe_n Input
  • QDR IV with Use Address Parity Bit=True
mem_ainv Output
  • QDR IV with Address Bus Inversion=True
mem_lda_n Output
  • QDR IV
mem_lda_b Output
  • QDR IV
mem_rwa_n Output
  • QDR IV
mem_rwb_n Output
  • QDR IV
mem_cfg_n Output
  • QDR IV
mem_lbk0_n Output
  • QDR IV
mem_lbk1_n Output
  • QDR IV
mem_dka Output
  • QDR IV
mem_dka_n Output
  • QDR IV
mem_dkb Output
  • QDR IV
mem_dkb_n Output
  • QDR IV
mem_qka Input
  • QDR IV
mem_qka_n Input
  • QDR IV
mem_qkb Input
  • QDR IV
mem_qkb_n Input
  • QDR IV
mem_dqa Bidirectional
  • QDR IV
mem_dqb Bidirectional
  • QDR IV
mem_dinva Bidirectional
  • QDR IV with Data Bus Inversion=True
mem_dinvb Bidirectional
  • QDR IV with Data Bus Inversion=True
Table 110.  Interface: oct_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
oct_rzqin Input Always available The On-Chip Termination (OCT) RZQ reference resistor input signal.

Export this interface to the top level for I/O assignments.

Table 111.  Interface: pll_ref_clk_clock_sink
Signals in Interface Interface Type Direction Availability Description
pll_ref_clk Clock Input Input
  • Core clock sharing=No Sharing / Master
The PLL reference clock input signal.

Connect this interface to the clock output of the clock source that matches the PLL reference clock frequency value set in the parameter editor.

Table 112.  Interface: status_conduit_end
Signals in Interface Interface Type Direction Availability Description
local_cal_success Conduit Output Always available The PHY calibration status output signals. When the local_cal_success signal is asserted, it indicates that the PHY calibration was successful. Otherwise, if local_cal_fail signal is asserted, it indicates that PHY calibration has failed.

Connect this interface to the conduit of the user logic block that requires the calibration status information, or leave it unconnected.

local_cal_fail

Related Information
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