External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

2.8.6. Package Migration

Package delays can be different for the same pin in different packages. If you want to use multiple migratable packages in your system, you should compensate for package skew as described in this topic. The information in this topic applies to Arria 10, Stratix V, and Stratix 10 devices.

Scenario 1

Your PCB is designed for multiple migratable devices, but you have only one device with which to go to production.

Assume two migratable packages, device A and device B, and that you want to go to production with device A. Follow these steps:

  1. Perform package deskew for device A.
  2. Compile your design for device A, with the Package Skew option enabled.
  3. Note the skews in the <core_name>.pin file for device A. Deskew these package skews with board trace lengths as described in the preceding examples.
  4. Recompile your design for device A.
  5. For device B, open the parameter editor and deselect the Package Deskew option.
  6. Calculate board skew parameters, only taking into account the board traces for device B, and enter that value into the parameter editor for device B.
  7. Regenerate the IP and recompile the design for device B.
  8. Verify that timing requirements are met for both device A and device B.

Scenario 2

Your PCB is designed for multiple migratable devices, and you want to go to production with all of them.

Assume you have device A and device B, and plan to use both devices in production. Follow these steps:

  1. Do not perform any package deskew compensation for either device.
  2. Compile a Quartus Prime design for device A with the Package Deskew option disabled, and ensure that all board skews are entered accurately.
  3. Verify that the Report DDR timing report meets your timing requirements.
  4. Compile a Quartus Prime design for device B with the Package Deskew option disabled, and ensure that all board skews are entered accurately.
  5. Verify that the Report DDR timing report meets your timing requirements.

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