8.4.4. Functional Simulation with VHDL
The top-level IP instance file is guaranteed to be written in VHDL; submodules can be deployed as Verilog/SystemVerilog (encrypted or plaintext) files, or VHDL files. ModelSim* - Intel FPGA Edition is not restricted to a single HDL language; however, some files may be encrypted to be excluded from the maximum unencrypted module limit of this tool.
Because the VHDL fileset consists of both VHDL and Verilog files, you must follow certain mixed-language simulation guidelines. The general guideline for mixed-language simulation is that you must always link the Verilog files (whether encrypted or not) against the Verilog version of the libraries, and the VHDL files (whether SimGen-generated or pure VHDL) against the VHDL libraries.
Simulation scripts for the Synopsys, Cadence, Aldec, and Mentor Graphics simulators are provided for you to run the example design. These simulation scripts are located in the following main folder locations:
Simulation scripts in the simulation folders are located as follows:
Simulation scripts in the <>_sim_folder are located as follows:
For more information about simulating Verilog HDL or VHDL designs using command lines, refer to the Mentor Graphics ModelSim* and QuestaSim Support chapter in volume 3 of the Quartus Prime Handbook.
Did you find the information on this page useful?