External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

2.8.2. DQ/DQS/DM Deskew4.2.3.1. DQ/DQS/DM Deskew

To get the package delay information, follow these steps:
  1. Select the FPGA DQ/DQS Package Skews Deskewed on Board checkbox on the Board Settings tab of the parameter editor.
  2. Generate your IP.
  3. Instantiate your IP in the project.
  4. Run Analysis and Synthesis in the Quartus Prime software. (Skip this step if you are using an Arria 10 device.)
  5. Run the <core_name>_p0_pin_assignment.tcl script. (Skip this step if you are using an Arria 10 device.)
  6. Compile your design.
  7. Refer to the All Package Pins compilation report, or find the pin delays displayed in the <core_name>.pin file.

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