External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.2.3. Arria V, Arria V GZ, Arria 10, Cyclone V, and Stratix V Timing paths

The following figures show block diagrams of the input data paths for Arria V, Arria V GZ, Cyclone V, and Stratix V devices, and for Arria 10 devices.
Figure 70. Arria V, Arria V GZ, Cyclone V, and Stratix V Input Data Path


The following figure shows a block diagram of the Arria 10 input data path.

Figure 71. Arria 10 Input Data Path


The following table lists all Arria V, Arria V GZ, Arria 10, Cyclone V, and Stratix V devices external memory interface timing paths.

Table 497.  Arria V, Arria V GZ, Arria 10, Cyclone V, and Stratix V External Memory Interface Timing Paths  (1) 

Timing Path

Circuit Category

Source

Destination

Read Data  (2)

Source‑Synchronous and Calibrated

Memory DQ, DQS Pins

DQ Capture Registers in IOE

Write Data  (2)

Source‑Synchronous and Calibrated

FPGA DQ, DM, DQS Pins

Memory DQ, DM, and DQS Pins

Address and command  (2)

Source-Synchronous

FPGA CK/CK# and Addr/Cmd Pins

Memory Input Pins

Clock-to-Strobe  (2)

Source-Synchronous

FPGA CK/CK# and DQS Output Pins

Memory Input Pins

Read Resynchronization  (2)

Source-Synchronous

IOE Capture Registers

Read FIFO in IOE

PHY & Controller Internal Paths  (2)

Internal Clock fMAX

Core Registers

Core Registers

i/O Toggle Rate  (3)

I/O – Data sheet

FPGA Output Pin

Memory Input Pins

Output Clock Specifications (Jitter, DCD)  (4)

I/O – Data sheet

FPGA Output Pin

Memory Input Pins

Notes to Table:

  1. This table lists the timing paths applicable for an interface between Arria V, Arria V GZ, Cyclone V, and Stratix V devices and half-rate SDRAM components.
  2. Timing margins for this path are reported by the TimeQuest Timing Analyzer Report DDR function.
  3. Intel recommends that you perform signal integrity simulations to verify I/O toggle rate.
  4. For output clock specifications, refer to the DC and Switching Characteristics chapter of the respective Device Handbook.

The following table lists the Arria 10 external memory interface timing paths.

Timing Path

Circuit Category

Source

Destination

Read Data (1)

Source-Synchronous and Calibrated

Memory DQ, DQS Pins

DQ Capture Registers in IOE

Write Data (1)

Source-Synchronous and Calibrated

FPGA DQ, DM, DQS Pins

Memory DQ, DM, and DQS Pins

Address and Command (1)

Source-Synchronous

FPGA CK/CK# and Address/Command Pins

Memory Input Pins

Clock-to-Strobe (1)

Source-Synchronous

FPGA CK/CK# and DQS Output Pins

Memory Input Pins

PHY & Controller Internal Paths

Internal Clock fmax

Core Registers

Core Registers

I/O Toggle Rate (2)

I/O Data sheet

FPGA Output Pin

Memory Input Pins

Output Clock Specifications (Jitter, DCD) (3)

I/O Data sheet

FPGA Output Pin

Memory Input Pins

Notes to Table:

  1. The Report DDR function in the TimeQuest Timing Analyzer reports the timing margins for this path.
  2. You should perform signal integrity simulations for verify I/O toggle rate.
  3. For output clock verifications, refer to the DC and Switching Characteristics chapter of the Intel® Arria 10 Device Handbook.

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