External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.4.8.2. Arria 10 EMIF IP RLDRAM 3 Parameters: Memory

Table 267.  Group: Memory / Topology
Display Name Identifier Description
Address width MEM_RLD3_ADDR_WIDTH Number of address pins.
CS# width MEM_RLD3_CS_WIDTH Number of chip selects of the memory interface.
Enable depth expansion using twin die package MEM_RLD3_DEPTH_EXPANDED Indicates whether to combine two RLDRAM3 devices to double the address space, resulting in more density.
DK width MEM_RLD3_DK_WIDTH Number of DK clock pairs of the memory interface. This is equal to the number of write data groups, and is automatically calculated based on the DQ width per device and whether width expansion is enabled.
DQ width per device MEM_RLD3_DQ_PER_DEVICE Specifies number of DQ pins per RLDRAM3 device and number of DQ pins per port per QDR IV device. Available widths for DQ are x18 and x36.
DQ width MEM_RLD3_DQ_WIDTH Number of data pins of the memory interface. Automatically calculated based on the DQ width per device and whether width expansion is enabled.
QK width MEM_RLD3_QK_WIDTH Number of QK output clock pairs of the memory interface. This is equal to the number of read data groups, and is automatically calculated based on the DQ width per device and whether width expansion is enabled.
Enable width expansion MEM_RLD3_WIDTH_EXPANDED Indicates whether to combine two memory devices to double the data bus width. With two devices, the interface supports a width expansion configuration up to 72-bits. For width expansion configuration, the address and control signals are routed to 2 devices.
Table 268.  Group: Memory / Mode Register Settings
Display Name Identifier Description
AREF protocol MEM_RLD3_AREF_PROTOCOL_ENUM Determines the mode register setting that controls the AREF protocol setting. The AUTO REFRESH (AREF) protocol is selected by setting mode register 1. There are two ways in which AREF commands can be issued to the RLDRAM, the memory controller can either issue bank address-controlled or multibank AREF commands. Multibank refresh protocol allows for the simultaneous refreshing of a row in up to four banks
Data Latency MEM_RLD3_DATA_LATENCY_MODE_ENUM Determines the mode register setting that controls the data latency. Sets both READ and WRITE latency (RL and WL).
ODT MEM_RLD3_ODT_MODE_ENUM Determines the mode register setting that controls the ODT setting.
Output drive MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM Determines the mode register setting that controls the output drive setting.
tRC MEM_RLD3_T_RC_MODE_ENUM Determines the mode register setting that controls the tRC(activate to activate timing parameter). Refer to the tRC table in the memory vendor data sheet. Set the tRC according to the memory speed grade and data latency. Full name of tRC
Write protocol MEM_RLD3_WRITE_PROTOCOL_ENUM Determines the mode register setting that controls the write protocol setting. When multiple bank (dual bank or quad bank) is selected, identical data is written to multiple banks.

Did you find the information on this page useful?

Characters remaining:

Feedback Message