External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents Arria 10 EMIF IP LPDDR3 Parameters: Memory

Table 188.  Group: Memory / Topology
Display Name Identifier Description
Bank address width MEM_LPDDR3_BANK_ADDR_WIDTH The number of bank address bits.
Number of clocks MEM_LPDDR3_CK_WIDTH Number of CK/CK# clock pairs exposed by the memory interface.
Column address width MEM_LPDDR3_COL_ADDR_WIDTH The number of column address bits.
Number of chip selects MEM_LPDDR3_DISCRETE_CS_WIDTH Total number of chip selects in the interface.
Enable DM pins MEM_LPDDR3_DM_EN Indicates whether interface uses data mask (DM) pins. This feature allows specified portions of the data bus to be written to memory (not available in x4 mode). One DM pin exists per DQS group
Number of DQS groups MEM_LPDDR3_DQS_WIDTH Specifies the total number of DQS groups in the interface. This value is automatically calculated as the DQ width divided by the number of DQ pins per DQS group.
DQ width MEM_LPDDR3_DQ_WIDTH Total number of DQ pins in the interface.
Row address width MEM_LPDDR3_ROW_ADDR_WIDTH The number of row address bits.
Table 189.  Group: Memory / Latency and Burst
Display Name Identifier Description
Burst length MEM_LPDDR3_BL Burst length of the memory device.
Data latency MEM_LPDDR3_DATA_LATENCY Determines the mode register setting that controls the data latency. Sets both READ and WRITE latency (RL and WL).
DQ ODT MEM_LPDDR3_DQODT The ODT setting for the DQ pins during writes.
Power down ODT MEM_LPDDR3_PDODT Turn on turn off ODT during power down.
WL set MEM_LPDDR3_WLSELECT The set of the currently selected write latency. Only certain memory devices support WL Set B. Refer to the WRITE Latency table in the memory vendor data sheet.

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