External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.4.3.2. Arria 10 EMIF IP DDR4 Parameters: Memory

Table 122.  Group: Memory / Topology
Display Name Identifier Description
DQS group of ALERT# MEM_DDR4_ALERT_N_DQS_GROUP Select the DQS group with which the ALERT# pin is placed.
ALERT# pin placement MEM_DDR4_ALERT_N_PLACEMENT_ENUM Specifies placement for the mem_alert_n signal. If you select "I/O Lane with Address/Command Pins", you can pick the I/O lane and pin index in the add/cmd bank with the subsequent drop down menus. If you select "I/O Lane with DQS Group", you can specify the DQS group with which to place the mem_alert_n pin. If you select "Automatically select a location", the IP automatically selects a pin for the mem_alert_n signal. If you select this option, no additional location constraints can be applied to the mem_alert_n pin, or a fitter error will result during compilation. For optimum signal integrity, you should choose "I/O Lane with Address/Command Pins". For interfaces containing multiple memory devices, it is recommended to connect the ALERT# pins together to the ALERT#pin on the FPGA.
Enable ALERT#/PAR pins MEM_DDR4_ALERT_PAR_EN Allows address/command calibration, which may provide better margins on the address/command bus. The alert_n signal is not accessible in the AFI or Avalon domains. This means there is no way to know whether a parity error has occurred during user mode. The parity pin is a dedicated pin in the address/command bank, but the alert_n pin can be placed in any bank that spans the memory interface. You should explicitly choose the location of the alert_n pin and place it in the address/command bank.
Bank address width MEM_DDR4_BANK_ADDR_WIDTH Specifies the number of bank address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of bank address pins needed for access to all available banks.
Bank group width MEM_DDR4_BANK_GROUP_WIDTH Specifies the number of bank group pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of bank group pins needed for access to all available bank groups.
Chip ID width MEM_DDR4_CHIP_ID_WIDTH Specifies the number of chip ID pins. Only applicable to registered and load-reduced DIMMs that use 3DS/TSV memory devices.
Number of clocks MEM_DDR4_CK_WIDTH Specifies the number of CK/CK# clock pairs exposed by the memory interface. Usually more than 1 pair is required for RDIMM/LRDIMM formats. The value of this parameter depends on the memory device selected; refer to the data sheet for your memory device.
Column address width MEM_DDR4_COL_ADDR_WIDTH Specifies the number of column address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of address pins needed for access to all available columns.
Number of chip selects per DIMM MEM_DDR4_CS_PER_DIMM Specifies the number of chip selects per DIMM.
Number of chip selects MEM_DDR4_DISCRETE_CS_WIDTH Specifies the total number of chip selects in the interface, up to a maximum of 4. This parameter applies to discrete components only.
Data mask MEM_DDR4_DM_EN Indicates whether the interface uses data mask (DM) pins. This feature allows specified portions of the data bus to be written to memory (not available in x4 mode). One DM pin exists per DQS group.
Number of DQS groups MEM_DDR4_DQS_WIDTH Specifies the total number of DQS groups in the interface. This value is automatically calculated as the DQ width divided by the number of DQ pins per DQS group.
DQ pins per DQS group MEM_DDR4_DQ_PER_DQS Specifies the total number of DQ pins per DQS group.
DQ width MEM_DDR4_DQ_WIDTH Specifies the total number of data pins in the interface. The maximum supported width is 144, or 72 in Ping Pong PHY mode.
Memory format MEM_DDR4_FORMAT_ENUM Specifies the format of the external memory device. The following formats are supported: Component - a Discrete memory device; UDIMM - Unregistered/Unbuffered DIMM where address/control, clock, and data are unbuffered; RDIMM - Registered DIMM where address/control and clock are buffered; LRDIMM - Load Reduction DIMM where address/control, clock, and data are buffered. LRDIMM reduces the load to increase memory speed and supports higher densities than RDIMM; SODIMM - Small Outline DIMM is similar to UDIMM but smaller in size and is typically used for systems with limited space. Some memory protocols may not be available in all formats.
Number of DIMMs MEM_DDR4_NUM_OF_DIMMS Total number of DIMMs.
Number of physical ranks per DIMM MEM_DDR4_RANKS_PER_DIMM Number of ranks per DIMM. For LRDIMM, this represents the number of physical ranks on the DIMM behind the memory buffer
Read DBI MEM_DDR4_READ_DBI Specifies whether the interface uses read data bus inversion (DBI). Enable this feature for better signal integrity and read margin. This feature is not available in x4 configurations.
Row address width MEM_DDR4_ROW_ADDR_WIDTH Specifies the number of row address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of address pins needed for access to all available rows.
Write DBI MEM_DDR4_WRITE_DBI Indicates whether the interface uses write data bus inversion (DBI). This feature provides better signal integrity and write margin. This feature is unavailable if Data Mask is enabled or in x4 mode.
Table 123.  Group: Memory / Latency and Burst
Display Name Identifier Description
Addr/CMD parity latency MEM_DDR4_AC_PARITY_LATENCY Additional latency incurred by enabling address/command parity check. Select a value to enable address/command parity with the latency associated with the selected value. Select Disable to disable address/command parity.
Memory additive CAS latency setting MEM_DDR4_ATCL_ENUM Determines the posted CAS additive latency of the memory device. Enable this feature to improve command and bus efficiency, and increase system bandwidth.
Burst Length MEM_DDR4_BL_ENUM Specifies the DRAM burst length which determines how many consecutive addresses should be accessed for a given read/write command.
Read Burst Type MEM_DDR4_BT_ENUM Indicates whether accesses within a given burst are in sequential or interleaved order. Select sequential if you are using the Intel-provided memory controller.
Memory CAS latency setting MEM_DDR4_TCL Specifies the number of clock cycles between the read command and the availability of the first bit of output data at the memory device. Overall read latency equals the additive latency (AL) + the CAS latency (CL). Overall read latency depends on the memory device selected; refer to the datasheet for your device.
Memory write CAS latency setting MEM_DDR4_WTCL Specifies the number of clock cycles from the release of internal write to the latching of the first data in at the memory device. This value depends on the memory device selected; refer to the datasheet for your device.
Table 124.  Group: Memory / Mode Register Settings
Display Name Identifier Description
Auto self-refresh method MEM_DDR4_ASR_ENUM Indicates whether to enable or disable auto self-refresh. Auto self-refresh allows the controller to issue self-refresh requests, rather than manually issuing self-refresh in order for memory to retain data.
Fine granularity refresh MEM_DDR4_FINE_GRANULARITY_REFRESH Increased frequency of refresh in exchange for shorter refresh. Shorter tRFC and increased cycle time can produce higher bandwidth.
Internal VrefDQ monitor MEM_DDR4_INTERNAL_VREFDQ_MONITOR Indicates whether to enable the internal VrefDQ monitor.
ODT input buffer during powerdown mode MEM_DDR4_ODT_IN_POWERDOWN Indicates whether to enable on-die termination (ODT) input buffer during powerdown mode.
Read preamble MEM_DDR4_READ_PREAMBLE Number of read preamble cycles. This mode register setting determines the number of cycles DQS (read) will go low before starting to toggle.
Self refresh abort MEM_DDR4_SELF_RFSH_ABORT Self refresh abort for latency reduction.
Temperature controlled refresh enable MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA Indicates whether to enable temperature controlled refresh, which allows the device to adjust the internal refresh period to be longer than tREFI of the normal temperature range by skipping external refresh commands.
Temperature controlled refresh range MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE Indicates temperature controlled refresh range where normal temperature mode covers 0C to 85C and extended mode covers 0C to 95C.
Write preamble MEM_DDR4_WRITE_PREAMBLE Write preamble cycles.

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