External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.4.3.7. Arria 10 EMIF IP DDR4 Parameters: Controller

Table 137.  Group: Controller / Low Power Mode
Display Name Identifier Description
Auto Power-Down Cycles CTRL_DDR4_AUTO_POWER_DOWN_CYCS Specifies the number of idle controller cycles after which the memory device is placed into power-down mode. You can configure the idle waiting time. The supported range for number of cycles is from 1 to 65534.
Enable Auto Power-Down CTRL_DDR4_AUTO_POWER_DOWN_EN Enable this parameter to have the controller automatically place the memory device into power-down mode after a specified number of idle controller clock cycles. The idle wait time is configurable. All ranks must be idle to enter auto power-down.
Table 138.  Group: Controller / Efficiency
Display Name Identifier Description
Address Ordering CTRL_DDR4_ADDR_ORDER_ENUM Controls the mapping between Avalon addresses and memory device addresses. By changing the value of this parameter, you can change the mappings between the Avalon-MM address and the DRAM address. (CS = chip select, CID = chip ID in 3DS/TSV devices, BG = bank group address, Bank = bank address, Row = row address, Col = column address)
Enable Auto-Precharge Control CTRL_DDR4_AUTO_PRECHARGE_EN Select this parameter to enable the auto-precharge control on the controller top level. If you assert the auto-precharge control signal while requesting a read or write burst, you can specify whether the controller should close (auto-precharge) the currently open page at the end of the read or write burst, potentially making a future access to a different page of the same bank faster.
Enable Reordering CTRL_DDR4_REORDER_EN Enable this parameter to allow the controller to perform command and data reordering. Reordering can improve efficiency by reducing bus turnaround time and row/bank switching time. Data reordering allows the single-port memory controller to change the order of read and write commands to achieve highest efficiency. Command reordering allows the controller to issue bank management commands early based on incoming patterns, so that the desired row in memory is already open when the command reaches the memory interface. For more information, refer to the Data Reordering topic in the EMIF Handbook.
Starvation limit for each command CTRL_DDR4_STARVE_LIMIT Specifies the number of commands that can be served before a waiting command is served. The controller employs a counter to ensure that all requests are served after a pre-defined interval -- this ensures that low priority requests are not ignored, when doing data reordering for efficiency. The valid range for this parameter is from 1 to 63. For more information, refer to the Starvation Control topic in the EMIF Handbook.
Enable Command Priority Control CTRL_DDR4_USER_PRIORITY_EN Select this parameter to enable user-requested command priority control on the controller top level. This parameter instructs the controller to treat a read or write request as high-priority. The controller attempts to fill high-priority requests sooner, to reduce latency. Connect this interface to the conduit of your logic block that determines when the external memory interface IP treats the read or write request as a high-priority command.
Table 139.  Group: Controller / Configuration, Status, and Error Handling
Display Name Identifier Description
Enable Auto Error Correction CTRL_DDR4_ECC_AUTO_CORRECTION_EN Specifies that the controller perform auto correction when a single-bit error is detected by the ECC logic.
Enable Error Detection and Correction Logic with ECC CTRL_DDR4_ECC_EN Enables error-correction code (ECC) for single-bit error correction and double-bit error detection. Your memory interface must have a width of 16, 24, 40, or 72 bits to use ECC. ECC is implemented as soft logic.
Enable Memory-Mapped Configuration and Status Register (MMR) Interface CTRL_DDR4_MMR_EN Enable this parameter to change or read memory timing parameters, memory address size, mode register settings, controller status, and request sideband operations.
Table 140.  Group: Controller / Data Bus Turnaround Time
Display Name Identifier Description
Additional read-to-read turnaround time (different ranks) CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a read of one logical rank to a read of another logical rank. This can resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists.
Additional read-to-write turnaround time (different ranks) CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a read of one logical rank to a write of another logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists.
Additional read-to-write turnaround time (same rank) CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a read to a write within the same logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists.
Additional write-to-read turnaround time (different ranks) CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a write of one logical rank to a read of another logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists.
Additional write-to-read turnaround time (same rank) CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a write to a read within the same logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists.
Additional write-to-write turnaround time (different ranks) CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS Specifies additional number of idle controller (not DRAM) cycles when switching the data bus from a write of one logical rank to a write of another logical rank. This can help resolve bus contention problems specific to your board topology. The value is added to the default which is calculated automatically. Use the default setting unless you suspect a problem exists.

Did you find the information on this page useful?

Characters remaining:

Feedback Message