External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

8.3.2. Arria® 10 Abstract PHY Simulation

The abstract PHY is a simulation model of the EMIF PHY that can decrease simulation time by 3-10 times. The abstract PHY replaces the lane and the external memory model with a single model containing an internal memory array. No switching of the I/Os to the external memory model occurs when simulating with the abstract PHY.

Abstract PHY reduces simulation time by two mechanisms:

  • The Nios processor has been disabled and replaced by HDL forces that are applied at the beginning of simulation. The HDL forces are a minimum set of configuration registers that allow the EMIF to be configured properly for simulation. The write and read latency values applied by the HDL forces are not representative of the post-calibration values applied to the EMIF running on hardware. However, as long as the customer logic is avalon- and afi-compliant, these values allow for successful RTL simulation.
  • The abstract PHY eliminates the need for full-speed clocks and therefore simulation of the abstract PHY does not require full-speed clock simulation events.

To use the abstract PHY, turn on Simulation Options > Abstract PHY for fast simulation on the Diagnostic tab. When you turn on the abstract PHY, the EMIF IP is configured as shown below. The PHY RTL and external memory model are disconnected from the data path and in their place is the abstract PHY containing an internal memory array. The abstract PHY is designed with no high-speed clocks, resulting in the removal of all high-speed clock simulator events.

Figure 66. Abstract PHY
Note: You cannot observe the external memory device signals when you are using the abstract PHY.

If the memory controller is normally part of the EMIF IP, it will continue to be instantiated and used when simulating with the abstract PHY. Because the memory controller regulates the throughput characteristics of data to the external memory interface, these throughput characteristics are maintained when simulating with the abstract PHY. It is important to understand that the abstract PHY is not a cycle-accurate mode of the EMIF IP, and therefore you should not expect to see cycle-accurate behavior.

The HDL forces are created by the Quartus Prime software at IP generation, and therefore you can run abstract PHY simulations immediately upon generation of the EMIF IP.

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