External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.4.3.10. About Memory Presets7.4.4.10. About Memory Presets7.4.5.9. About Memory Presets7.4.6.9. About Memory Presets7.4.7.9. About Memory Presets7.4.8.8. About Memory Presets7.5.3.10. About Memory Presets7.5.4.10. About Memory Presets7.5.5.10. About Memory Presets7.5.6.9. About Memory Presets7.5.7.9. About Memory Presets7.5.8.8. About Memory Presets

Presets help simplify the process of copying memory parameter values from memory device data sheets to the EMIF parameter editor.

For DDRx protocols, the memory presets are named using the following convention:

PROTOCOL-SPEEDBIN LATENCY FORMAT-AND-TOPOLOGY CAPACITY (INTERNAL-ORGANIZATION)

For example, the preset named DDR4-2666U CL18 Component 1CS 2Gb (512Mb x 4) refers to a DDR4 x4 component rated at the DDR4-2666U JEDEC speed bin, with nominal CAS latency of 18 cycles, one chip-select, and a total memory space of 2Gb. The JEDEC memory specification defines multiple speed bins for a given frequency (that is, DDR4-2666U and DDR4-2666V). You may be able to determine the exact speed bin implemented by your memory device using its nominal latency. When in doubt, contact your memory vendor.

For RLDRAMx and QDRx protocols, the memory presets are named based on the vendor's device part number.

When the preset list does not contain the exact configuration required, you can still minimize data entry by selecting the preset closest to your configuration and then modify parameters as required.

Prior to production you should always review the parameter values to ensure that they match your memory device data sheet, regardless of whether a preset is used or not. Incorrect memory parameters can cause functional failures.

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