External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.5.3.4. Stratix 10 EMIF IP DDR4 Parameters: FPGA I/O

You should use Hyperlynx* or similar simulators to determine the best settings for your board. Refer to the EMIF Simulation Guidance wiki page for additional information.
Table 332.  Group: FPGA IO / FPGA IO Settings
Display Name Identifier Description
Use default I/O settings PHY_DDR4_DEFAULT_IO Specifies that a legal set of I/O settings are automatically selected. The default I/O settings are not necessarily optimized for a specific board. To achieve optimal signal integrity, perform I/O simulations with IBIS models and enter the I/O settings manually, based on simulation results.
Voltage PHY_DDR4_IO_VOLTAGE The voltage level for the I/O pins driving the signals between the memory device and the FPGA memory interface.
Periodic OCT re-calibration PHY_USER_PERIODIC_OCT_RECAL_ENUM Specifies that the system periodically recalibrate on-chip termination (OCT) to minimize variations in termination value caused by changing operating conditions (such as changes in temperature). By recalibrating OCT, I/O timing margins are improved. When enabled, this parameter causes the PHY to halt user traffic about every 0.5 seconds for about 1900 memory clock cycles, to perform OCT recalibration. Efficiency is reduced by about 1% when this option is enabled.
Table 333.  Group: FPGA IO / Address/Command
Display Name Identifier Description
I/O standard PHY_DDR4_USER_AC_IO_STD_ENUM Specifies the I/O electrical standard for the address/command pins of the memory interface. The selected I/O standard configures the circuit within the I/O buffer to match the industry standard.
Output mode PHY_DDR4_USER_AC_MODE_ENUM This parameter allows you to change the current drive strength or termination settings for the selected I/O standard. Perform board simulation with IBIS models to determine the best settings for your design.
Slew rate PHY_DDR4_USER_AC_SLEW_RATE_ENUM Specifies the slew rate of the address/command output pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the address and command signals.
Table 334.  Group: FPGA IO / Memory Clock
Display Name Identifier Description
I/O standard PHY_DDR4_USER_CK_IO_STD_ENUM Specifies the I/O electrical standard for the memory clock pins. The selected I/O standard configures the circuit within the I/O buffer to match the industry standard.
Output mode PHY_DDR4_USER_CK_MODE_ENUM This parameter allows you to change the current drive strength or termination settings for the selected I/O standard. Perform board simulation with IBIS models to determine the best settings for your design.
Slew rate PHY_DDR4_USER_CK_SLEW_RATE_ENUM Specifies the slew rate of the address/command output pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the address and command signals.
Table 335.  Group: FPGA IO / Data Bus
Display Name Identifier Description
Use recommended initial Vrefin PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN Specifies that the initial Vrefin setting is calculated automatically, to a reasonable value based on termination settings.
Input mode PHY_DDR4_USER_DATA_IN_MODE_ENUM This parameter allows you to change the input termination settings for the selected I/O standard. Perform board simulation with IBIS models to determine the best settings for your design.
I/O standard PHY_DDR4_USER_DATA_IO_STD_ENUM Specifies the I/O electrical standard for the data and data clock/strobe pins of the memory interface. The selected I/O standard option configures the circuit within the I/O buffer to match the industry standard.
Output mode PHY_DDR4_USER_DATA_OUT_MODE_ENUM This parameter allows you to change the output current drive strength or termination settings for the selected I/O standard. Perform board simulation with IBIS models to determine the best settings for your design.
Initial Vrefin PHY_DDR4_USER_STARTING_VREFIN Specifies the initial value for the reference voltage on the data pins (Vrefin). This value is entered as a percentage of the supply voltage level on the I/O pins. The specified value serves as a starting point and may be overridden by calibration to provide better timing margins. If you choose to skip Vref calibration (Diagnostics tab), this is the value that is used as the Vref for the interface.
Table 336.  Group: FPGA IO / PHY Inputs
Display Name Identifier Description
PLL reference clock I/O standard PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM Specifies the I/O standard for the PLL reference clock of the memory interface.
RZQ I/O standard PHY_DDR4_USER_RZQ_IO_STD_ENUM Specifies the I/O standard for the RZQ pin used in the memory interface.
RZQ resistor PHY_RZQ Specifies the reference resistor used to calibrate the on-chip termination value. You should connect the RZQ pin to GND through an external resistor of the specified value.

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