External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

1.1.17. LPDDR2 and LPDDR3 Command and Address Signal

All LPDDR2 and LPDDR3 devices use double data rate architecture on the command/address bus to reduce the number of input pins in the system. The 10-bit command/address bus contains command, address, and bank/row buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edges of the clock.

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