External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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2.7.2. Layout Guidelines for DDR3 and DDR4 SDRAM Interfaces

The following table lists DDR3 and DDR4 SDRAM layout guidelines.

Unless otherwise specified, the guidelines in the following table apply to the following topologies:

  • DIMM—UDIMM topology
  • DIMM—RDIMM topology
  • DIMM—LRDIMM topology
  • Not all versions of the Quartus Prime software support LRDIMM.
  • Discrete components laid out in UDIMM topology
  • Discrete components laid out in RDIMM topology

These guidelines are recommendations, and should not be considered as hard requirements. You should perform signal integrity simulation on all the traces to verify the signal integrity of the interface.

Unless stated otherwise, the following guidelines apply to all devices that support DDR3 or DDR4, including Arria 10 and Stratix 10.

For information on the simulation flow for 28nm products, refer to http://www.alterawiki.com/wiki/Measuring_Channel_Signal_Integrity.

For information on the simulation flow for Arria 10 products, refer to http://www.alterawiki.com/wiki/Arria_10_EMIF_Simulation_Guidance.

http://www.altera.com/technology/memory/estimator/mem-emif-index.html

For supported frequencies and topologies, refer to the External Memory Interface Spec Estimator http://www.altera.com/technology/memory/estimator/mem-emif-index.html.

For frequencies greater than 800 MHz, when you are calculating the delay associated with a trace, you must take the FPGA package delays into consideration. For more information, refer to Package Deskew.

For device families that do not support write leveling, refer to Layout Guidelines for DDR2 SDRAM Interfaces.

Table 34.  DDR3 and DDR4 SDRAM Layout Guidelines   (1)

Parameter

Guidelines

Decoupling Parameter

  • Make VTT voltage decoupling close to the components and pull-up resistors.
  • Connect decoupling caps between VTT and VDD using a 0.1F cap for every other VTT pin.
  • Use a 0.1 uF cap and 0.01 uF cap for every VDDQ pin.

Maximum Trace Length  (2)

  • Even though there are no hard requirements for minimum trace length, you need to simulate the trace to ensure the signal integrity. Shorter routes result in better timing.
  • For DIMM topology only:
  • Maximum trace length for all signals from FPGA to the first DIMM slot is 4.5 inches.
  • Maximum trace length for all signals from DIMM slot to DIMM slot is 0.425 inches.
  • For discrete components only:
  • Maximum trace length for address, command, control, and clock from FPGA to the first component must not be more than 7 inches.
  • Maximum trace length for DQ, DQS, DQS#, and DM from FPGA to the first component is 5 inches.

General Routing

  • Route over appropriate VCC and GND planes.
  • Keep signal routing layers close to GND and power planes.
Spacing Guidelines
  • Avoid routing two signal layers next to each other. Always make sure that the signals related to memory interface are routed between appropriate GND or power layers.
  • For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) for these traces. (Where H is the vertical distance to the closest return path for that particular trace.)
  • For Address/Command/Control traces: Maintain at least 3H spacing between the edges (air-gap) these traces. (Where H is the vertical distance to the closest return path for that particular trace.)
  • For Clock traces: Maintain at least 5H spacing between two clock pair or a clock pair and any other memory interface trace. (Where H is the vertical distance to the closest return path for that particular trace.)

Clock Routing

  • Route clocks on inner layers with outer-layer run lengths held to under 500 mils (12.7 mm).
  • Route clock signals in a daisy chain topology from the first SDRAM to the last SDRAM. The maximum length of the first SDRAM to the last SDRAM must not exceed 0.69 tCK for DDR3 and 1.5 tCK for DDR4. For different DIMM configurations, check the appropriate JEDEC specification.
  • These signals should maintain the following spacings:
  • Clocks should maintain a length-matching between clock pairs of ±5 ps.
  • Clocks should maintain a length-matching between positive (p) and negative (n) signals of ±2 ps, routed in parallel.
  • Space between different pairs should be at least two times the trace width of the differential pair to minimize loss and maximize interconnect density.
  • To avoid mismatched transmission line to via, Intel® recommends that you use Ground Signal Signal Ground (GSSG) topology for your clock pattern—GND|CLKP|CKLN|GND.
  • Route all addresses and commands to match the clock signals to within ±20 ps to each discrete memory component. Refer to the following figure.

Address and Command Routing

  • Route address and command signals in a daisy chain topology from the first SDRAM to the last SDRAM. The maximum length of the first SDRAM to the last SDRAM must not be more than 0.69 tCK for DDR3 and 1.5 tCK for DDR4. For different DIMM configurations, check the appropriate JEDEC specifications.
  • UDIMMs are more susceptible to cross-talk and are generally noisier than buffered DIMMs. Therefore, route address and command signals of UDIMMs on a different layer than data signals (DQ) and data mask signals (DM) and with greater spacing.
  • Do not route differential clock (CK) and clock enable (CKE) signals close to address signals.
  • Route all addresses and commands to match the clock signals to within ±20 ps to each discrete memory component. Refer to the following figure.

DQ, DM, and DQS Routing Rules

  • All the trace length matching requirements are from the FPGA package ball to the SDRAM package ball, which means you must consider trace mismatching on different DIMM raw cards.
  • Match in length all DQ, DQS, and DM signals within a given byte-lane group with a maximum deviation of ±10 ps.
  • Ensure to route all DQ, DQS, and DM signals within a given byte-lane group on the same layer to avoid layer to layer transmission velocity differences, which otherwise increase the skew within the group.
  • Do not count on FPGAs to deskew for more than 20 ps of DQ group skew. The skew algorithm only removes the following possible uncertainties:
    • Minimum and maximum die IOE skew or delay mismatch
    • Minimum and maximum device package skew or mismatch
    • Board delay mismatch of 20 ps
    • Memory component DQ skew mismatch
    • Increasing any of these four parameters runs the risk of the deskew algorithm limiting, failing to correct for the total observed system skew. If the algorithm cannot compensate without limiting the correction, timing analysis shows reduced margins.
  • For memory interfaces with leveling, the timing between the DQS and clock signals on each device calibrates dynamically to meet tDQSS. To make sure the skew is not too large for the leveling circuit’s capability, follow these rules:
    • Propagation delay of clock signal must not be shorter than propagation delay of DQS signal at every device: (CKi) – DQSi > 0; 0 < i < number of components – 1 . For DIMMs, ensure that the CK trace is longer than the longest DQS trace at the DIMM connector.
    • Total skew of CLK and DQS signal between groups is less than one clock cycle: (CKi+ DQSi) max – (CKi+ DQSi) min < 1 × tCK(If you are using a DIMM topology, your delay and skew must take into consideration values for the actual DIMM.)

Spacing Guidelines

  • Avoid routing two signal layers next to each other. Always ensure that the signals related to the memory interface are routed between appropriate GND or power layers.
  • For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return path for that particular trace.
  • For Address/Command/Control traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return path for that particular trace.
  • For Clock traces: Maintain at least 5H spacing between two clock pairs or a clock pair and any other memory interface trace, where H is the vertical distance to the closest return path for that particular trace.

Quartus Prime Software Settings for Board Layout

  • To perform timing analyses on board and I/O buffers, use third party simulation tool to simulate all timing information such as skew, ISI, crosstalk, and type the simulation result into the UniPHY board setting panel.
  • Do not use advanced I/O timing model (AIOT) or board trace model unless you do not have access to any third party tool. AIOT provides reasonable accuracy but tools like HyperLynx provide better results.

Notes to Table:

  1. For point-to-point and DIMM interface designs, refer to the Micron website, www.micron.com.
  2. For better efficiency, the UniPHY IP requires faster turnarounds from read commands to write.

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