External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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7.4.6.4. Arria 10 EMIF IP QDR-IV Parameters: Mem Timing

These parameters should be read from the table in the datasheet associated with the speed bin of the memory device (not necessarily the frequency at which the interface is running).
Table 225.  Group: Mem Timing / Parameters dependent on Speed Bin
Display Name Identifier Description
Speed bin MEM_QDR4_SPEEDBIN_ENUM The speed grade of the memory device used. This parameter refers to the maximum rate at which the memory device is specified to run.
tASH MEM_QDR4_TASH_PS tASH provides the setup/hold window requirement for the address bus in relation to the CK clock. Because the individual signals in the address bus may not be perfectly aligned with each other, this parameter describes the intersection window for all the individual address signals setup/hold margins.
tCKDK_max MEM_QDR4_TCKDK_MAX_PS tCKDK_max refers to the maximum skew from the memory clock (CK) to the write strobe (DK).
tCKDK_min MEM_QDR4_TCKDK_MIN_PS tCKDK_min refers to the minimum skew from the memory clock (CK) to the write strobe (DK).
tCKQK_max MEM_QDR4_TCKQK_MAX_PS tCKQK_max refers to the maximum skew from the memory clock (CK) to the read strobe (QK).
tCSH MEM_QDR4_TCSH_PS tCSH provides the setup/hold window requirement for the control bus (LD#, RW#) in relation to the CK clock. Because the individual signals in the control bus may not be perfectly aligned with each other, this parameter describes the intersection window for all the individual control signals setup/hold margins.
tISH MEM_QDR4_TISH_PS tISH provides the setup/hold window requirement for the entire data bus (DK or DINV) in all the data groups with respect to the DK clock. After deskew calibration, this parameter describes the intersection window for all the individual data bus signals setup/hold margins.
tQH MEM_QDR4_TQH_CYC tQH specifies the output hold time for the DQ/DINV in relation to QK.
tQKQ_max MEM_QDR4_TQKQ_MAX_PS tQKQ_max describes the maximum skew between the read strobe (QK) clock edge to the data bus (DQ/DINV) edge.

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