External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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6.4.3.7. Ping-Pong PHY Implementation

The Ping Pong PHY feature instantiates two hard memory controllers—one for the primary interface and one for the secondary interface. The hard memory controller I/O bank of the primary interface is used for address and command and is always adjacent and above the hard memory controller I/O bank of the secondary interface. All four lanes of the primary hard memory controller I/O bank are used for address and command.

When you use Ping Pong PHY, the EMIF IP exposes two independent Avalon® -MM interfaces to user logic; these interfaces correspond to the two hard memory controllers inside the interface. Each Avalon® -MM interface has its own set of clock and reset signals. Refer to Platform Designer Interfaces for more information on the additional signals exposed by Ping Pong PHY interfaces.

For pin allocation information for Intel® Stratix® 10 devices, refer to External Memory Interface Pin Information for Intel® Stratix® 10 Devices on www.altera.com.

Additional Requirements for DDR3 and DDR4 Ping-Pong PHY Interfaces

If you are using Ping Pong PHY with a DDR3 or DDR4 external memory interface on an Intel® Stratix® 10 device, follow these guidelines:

  • The address and command I/O bank must not contain any DQS group.
  • I/O banks that are above the address and command I/O bank must contain only data pins of the primary interface—that is, the interface with the lower DQS group indices.
  • The I/O bank immediately below the address and command I/O bank must contain at least one DQS group of the secondary interface—that is, the interface with the higher DQS group indices. This I/O bank can, but is not required to, contain DQS groups of the primary interface.
  • I/O banks that are two or more banks below the address and command I/O bank must contain only data pins of the secondary interface.

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