External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public
Document Table of Contents

7.5.2.3. How to Enter Calculated Channel Signal Integrity Values

You should enter calculated channel loss values in the Channel Signal Integrity section of the Board (or Board Timing) tab of the parameter editor.

For Intel® Stratix® 10 external memory interfaces, the default channel loss displayed in the parameter editor is based on the selected configuration (different values for single rank versus dual rank), and on internal Intel reference boards. You should replace the default value with the value that you calculate.

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