External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.1. Intel® Stratix® 10 Calibration Stages

At a high level, the calibration routine consists of address and command calibration, read calibration, and write calibration.

The stages of calibration vary, depending on the protocol of the external memory interface.

Table 6.  Calibration Stages by Protocol
Stage DDR4 DDR3 RLDRAM 3 QDR-IV QDR II/II+
Address and command
Leveling Yes Yes
Deskew Yes Yes
Read
DQSen Yes Yes Yes Yes Yes
Deskew Yes Yes Yes Yes Yes
VREF-In Yes Yes
LFIFO Yes Yes Yes Yes Yes
Write
Leveling Yes Yes Yes Yes
Deskew Yes Yes Yes Yes Yes
VREF-Out Yes

Did you find the information on this page useful?

Characters remaining:

Feedback Message