External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1.13. afi_clk for DDR3

AFI clock interface

Table 24.  Interface: afi_clkInterface type: Clock Output
Port Name Direction Description
afi_clk Output Clock for the Altera PHY Interface (AFI)