External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.2.4.5. Vref Margining Tab

The VREF Margining feature sweeps different Vref-in and Vref-out settings. At each VREF value, calibration finds the margin on each pin.

You can choose to apply this margining tool to both or only one of the directions ( VREF-in or VREF-out) using the checkboxes near the Run Vref Margining button. The tool reports the passing delay margins for each pin, at each VREF value, for each direction. The Pin ID corresponds to the DQ index on the interface (for example, Pin ID=0 refers to DQ0 on the memory interface).

Figure 146. VREF Margining

Note: Reports can also be viewed graphically; for information, refer to View Diagrams in Eye Viewer.

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