External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
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8.1.4. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Timing

These parameters should be read from the table in the datasheet associated with the speed bin of the memory device (not necessarily the frequency at which the interface is running).
Table 270.  Group: Mem Timing
Display Name Description
Speed bin The speed grade of the memory device used. This parameter refers to the maximum rate at which the memory device is specified to run. (Identifier: MEM_QDR2_SPEEDBIN_ENUM)
tRL tRL refers to the QDR memory specific read latency. This parameter describes the length of time after a Read command has been registered on the rising edge of the Write Clock (K) at the QDR memory before the first piece of read data (Q) can be expected at the output of the memory. It is measured in Write Clock (K) cycles. The Read Latency is specific to a QDR memory device and cannot be modified to a different value. The Read Latency (tRL) can have the following values: 1.5, 2, 2,5 clk cycles. (Identifier: MEM_QDR2_TRL_CYC)
tSA tSA refers to the setup time for the address and command bus (A) before the rising edge of the clock (K). The address and command bus must be stable for at least tSA before the rising edge of K. (Identifier: MEM_QDR2_TSA_NS)
tHA tHA refers to the hold time after the rising edge of the clock (K) to the address and command control bus (A). The address and command control bus must remain stable for at least tHA after the rising edge of K. (Identifier: MEM_QDR2_THA_NS)
tSD tSD refers to the setup time for the data bus (D) before the rising edge of the clock (K). The data bus must be stable for at least tSD before the rising edge of K. (Identifier: MEM_QDR2_TSD_NS)
tHD tHD refers to the hold time after the rising edge of the clock (K) to the data bus (D). The data bus must remain stable for at least tHD after the rising edge of K. (Identifier: MEM_QDR2_THD_NS)
tCQD tCQD refers to the maximum time expected between an echo clock edge and valid data on the Read Data bus (Q). (Identifier: MEM_QDR2_TCQD_NS)
tCQDOH tCQDOH refers to the minimum time expected between the echo clock (CQ or CQ#) edge and the last of the valid Read data (Q). (Identifier: MEM_QDR2_TCQDOH_NS)
Internal Jitter QDRII internal jitter. (Identifier: MEM_QDR2_INTERNAL_JITTER_NS)
tCQH tCQH describes the time period during which the echo clock (CQ, #CQ) is considered logically high. (Identifier: MEM_QDR2_TCQH_NS)
tCCQO tCCQO describes the skew between the rising edge of the C clock to the rising edge of the echo clock (CQ) in QDRII memory devices. (Identifier: MEM_QDR2_TCCQO_NS)

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