External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.1. Intel® Stratix® 10 EMIF Architecture: I/O Subsystem

Depending on the Intel® Stratix® 10 device, the I/O subsystem consists of either two or three columns inside the core.
Figure 2. Stratix 10 I/O Subsystem

The I/O subsystem provides the following features:

  • General-purpose I/O registers and I/O buffers
  • On-chip termination control (OCT)
  • I/O PLLs for external memory interfaces and user logic
  • Low-voltage differential signaling (LVDS)
  • External memory interface components, as follows:
    • Hard memory controller
    • Hard PHY
    • Hard Nios processor and calibration logic
    • DLL

Did you find the information on this page useful?

Characters remaining:

Feedback Message