External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2. Intel® Stratix® 10 EMIF IP Design Checklist

Refer to the following checklist as a quick reference for information about each step in the EMIF design flow.

Table 2.  EMIF Design Checklist
Design Step Description Resources
Select an FPGA Not all Intel FPGAs support all memory types and configurations. To help with the FPGA selection process, refer to these resources.
Parameterize the IP Correct IP parameterization is important for good EMIF IP operation. These resources define the memory parameters during IP generation.
Generate initial IP and example design After you have parameterized the EMIF IP, you can generate the IP, along with an optional example design. Refer to the Quick-Start Guide for a walkthrough of this process.
Perform functional simulation Simulation of the EMIF design helps to determine correct operation. These resources explain how to perform simulation and what differences exist between simulation and hardware implementation.
Make pin assignments For guidance on pin placement, refer to these resources.
Perform board simulation Board simulation helps determine optimal settings for signal integrity, drive strength, as well as sufficient timing margins and eye openings. For guidance on board simulation, refer to these resources.
Update board parameters in the IP Board simulation is important to determine optimal settings for signal integrity, drive strength, and sufficient timing margins and eye openings. For guidance on board simulation refer to the mentioned resources.
Verify timing closure For information regarding compilation, system-level timing closure and timing reports refer to the Timing Closure section of this User Guide.
Run the design on hardware For instructions on how to program a FPGA refer to the Quick-Start Guide section of this User Guide.
Debug issues with preceding steps Operational problems can generally be attributed to one of the following: interface configuration, pin/resource planning, signal integrity, or timing. These resources contain information on typical debug procedures and available tools to help diagnose hardware issues.

Did you find the information on this page useful?

Characters remaining:

Feedback Message