External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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4.1.1.15. afi for DDR3

Altera PHY Interface (AFI)

Table 26.  Interface: afiInterface type: Conduit
Port Name Direction Description
afi_cal_success Output Signals calibration successful completion
afi_cal_fail Output Signals calibration failure
afi_cal_req Input When asserted, the interface is recalibrated
afi_rlat Output Latency in afi_clk cycles between read command and read data valid
afi_wlat Output Latency in afi_clk cycles between write command and write data valid
afi_addr Input Address
afi_ba Input Bank address
afi_cke Input Clock enable
afi_cs_n Input Chip select
afi_rm Input Rank multiplication for LRDIMM
afi_odt Input On-die termination
afi_ras_n Input RAS command
afi_cas_n Input CAS command
afi_we_n Input WE command
afi_rst_n Input Asynchronous reset
afi_dm Input Write data mask
afi_dqs_burst Input Asserted by the controller to enable the output DQS signal
afi_wdata_valid Input Asserted by the controller to indicate that afi_wdata contains valid write data
afi_wdata Input Write data
afi_rdata_en_full Input Asserted by the controller to indicate the amount of relevant read data expected
afi_rdata Output Read data
afi_rdata_valid Output Asserted by the PHY to indicate that afi_rdata contains valid read data
afi_rrank Input Asserted by the controller to indicate which rank is being read from, to control shadow register switching
afi_wrank Input Asserted by the controller to indicate which rank is being written to, to control shadow register switching

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