External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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3.4.1.2. Hard Memory Controller Main Control Path

The main control path performs the following functions:
  • Contains the command processing pipeline.
  • Monitors all the timing parameters.
  • Keeps track of dependencies between memory access commands.
  • Guards against memory access hazards.
Table 8.  Main Control Path Components
Component Description
Input interface
  • Accepts memory access commands from the core logic at half or quarter rate.
  • Uses the Avalon® -MM protocol.
  • You can connect the Avalon® -MM interface to the AXI bus master in the Platform Designer (formerly Qsys). To connect the Avalon® -MM interface, implement the AXI bus master as a Platform Designer component and connect the AXI bus master to the Avalon® -MM slave. The Platform Designer interconnect performs the bus translation between the AXI and Avalon® -MM bus interfaces.
  • To support all bypass modes and keep the port count minimum, the super set of all port lists is used as the physical width. Ports are shared among the bypass modes.
Command generator and burst adapter
  • Drains your commands from the input interface and feeds them to the timing bank pool.
  • If read-modify-write is required, inserts the necessary read-modify-write read and write commands into the stream.
  • The burst adapter chops your arbitrary burst length to the number specified by the memory types.
Timing Bank Pool
  • Key component in the memory controller.
  • Sets parallel queues to track command dependencies.
  • Signals the ready status of each command being tracked to the arbiter for the final dispatch.
  • Big scoreboard structure. The number of entries is currently sized to 8 where it monitors up to 8 commands at the same time.
  • Handles the memory access hazards such as Read After Write (RAW), Write After Read (WAR), and Write After Write (WAW), while part of the timing constraints are being tracked.
  • Assist the arbiter in reordering row commands and column commands.
  • When the pool is full, a flow control signal is sent back upstream to stall the traffic.
Arbiter
  • Enforces the arbitration rules.
  • Performs the final arbitration to select a command from all ready commands, and issues the selected command to the memory.
  • Supports Quasi-1T mode for half rate mode.
  • For the quasi modes, a row command must be paired with a column command.
Global Timer

Tracks the global timing constraints including:

  • tFAW—the Four Activates Window parameter that specifies the time period in which only four activate commands are allowed.
  • tRRD—the delay between back-to-back activate commands to different banks.
  • Some of the bus turnaround time parameters.
MMR/IOCSR
  • The host of all the configuration registers.
  • Uses Avalon® -MM bus to talk to the core.
  • Core logic can read and write all the configuration bits.
  • The debug bus is routed to the core through this block.
Sideband

Executes the refresh and power down features.

ECC controller

Although ECC encoding and decoding is performed in soft logic1, the ECC controller maintains the read-modify-write state machine in the hard solution.

AFI interface

The memory controller communicates with the PHY using this interface.

1 ECC encoding and decoding is performed in soft logic to exempt the hard connection from routing data bits to a central ECC calculation location. Routing data to a central location removes the modular design benefits and reduces flexibility.

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