External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022

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Document Table of Contents Slew Rates

For optimum timing margins and best signal integrity for the address, command, and memory clock signals, you should generally use fast slew rates and external terminations.

In board simulation, fast slew rates may show a perceived signal integrity problem, such as reflections or a nonmonotonic waveform in the SSTL I/O switching region. Such indications may cause you to consider using slow slew rate options for either the address and command signals or the memory clock, or both.

If you set the FPGA I/O tab parameter options > Address/Command > Slew Rate and Memory Clock > Slew Rate parameters to different values, a warning message appears: .

Warning: .emif_0: When the address/command signals and the memory clock signals do not use the same slew rate setting, signals using the "Slow" setting are delayed relative to signals using "Fast" setting. For accurate timing analysis, you must perform I/O simulation and manually include the delay as board skew. To avoid the issue, use the same slew rate setting for both address/command signals and memory clock signals whenever possible.
Note: The warning message applies only to board-level simulation, and does not require any delay adjustments in the PCB design or Board tab parameter settings.

Due to limitations of the IBIS model correlation tolerance and the accuracy of the board simulation model, it is possible for signal integrity problems to appear when using fast slew rate during simulation but not occur during operation on hardware. If you observe a signal integrity problem during simulation with a fast slew rate, use an oscilloscope to view the signal at that point in hardware, to verify whether the problem exists on hardware, or only in simulation.

If the signal integrity problem exists on hardware as well as in simulation, using different slew rates for the address and command signals and the clock remains a valid approach, and the address and command calibration stage will help to improve the address and command to clock setup and hold time margins.