External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

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ID 683741
Date 3/11/2022
Public
Document Table of Contents

4.4.3. dramtiming0

address=20(32 bit)

Field Bit High Bit Low Description Access
cfg_tcl 6 0 Memory read latency. Read
Reserved 31 7 Reserved. Read

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