External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.2.7.4. Debugging DQS Enable Failure

  1. Verify that the correct resistor is connected between the RZQ pin of the FPGA and GND.
  2. Verify that the correct resistor is connected between the ZQ pin of the memory component and GND.
  3. Verify that there is no connectivity problem preventing the memory component from receiving the back-to-back READ commands correctly.
  4. Verify that there is no connectivity problem preventing the DQS/DQSn pins on the FPGA from receiving the DQS/DQSn signals correctly.
  5. Verify that the address and command pins are correctly connected between the FPGA and the memory device or DIMM. (Note that passing the address and command leveling and deskew does not necessarily mean that these signals are connected properly (i.e no swap of signals).

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