External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.8. Using the Default Traffic Generator

A Traffic Generator (TG) IP instance is present in any EMIF Design Example; its purpose is to connect an EMIF IP instance via the ctrl_amm_* port(s) and send sample traffic (writes and reads) through the EMIF to the memory. The TG traffic pattern is parameterizable, and it is configured to start once TG comes out of reset.

The Traffic Generator also compares the written data and the read data, and sets one of the following status bits:

  • traffic_gen_pass (TGP ISSP): Indicates that all write and read commands were sent to the EMIF, all read responses were received, and all writes and reads matched as expected.
  • traffic_gen_fail (TGF ISSP): Indicates that all write and read commands were sent to the EMIF, all read responses were received, but one or more write-read mismatches have occurred.
  • traffic_gen_timeout (TGT ISSP): Indicates that one or more of the expected read responses were not received.

Figure 168. EMIF Design Example Overview

For general information about the generated EMIF design example, refer to the External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide.

You can use the traffic generator for a variety of analysis and debugging applications, including the following:

  • Verifying that an external memory interface is configured and working correctly, in simulation and in hardware.
  • Evaluating the stability of the interface, as well as the calibration results. (Refer to the Driver Margining Tab topic.)
  • Isolating hardware issues such as single pin failures.
  • Distinguishing between read failures and write failures.
  • Running infinite traffic for hardware debugging.
  • Measuring the efficiency of the interface.

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