External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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7.5.4.4. Spacing Guidelines

This topic provides recommendations for minimum spacing between board traces for various signal traces.

Spacing Guidelines for DQ, DQS, and DM Traces

Maintain a minimum of 3H spacing between the edges (air-gap) of these traces. (Where H is the vertical distance to the closest return path for that particular trace.)

Spacing Guidelines for Address and Command and Control Traces

Maintain at least 3H spacing between the edges (air-gap) of these traces. (Where H is the vertical distance to the closest return path for that particular trace.)



Spacing Guidelines for Clock Traces

Maintain at least 5H spacing between two clock pair or a clock pair and any other memory interface trace. (Where H is the vertical distance to the closest return path for that particular trace.)