External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.4.3. Communicating Directly to the Legacy Efficiency Monitor and Protocol Checker

When you export the Legacy Efficiency Monitor, a CSR Avalon® slave interface is added to enable communication directly to the Efficiency Monitor and Protocol Checker without using the EMIF Debug Toolkit. You can create user logic to retrieve the efficiency statistic of the interface. The following table lists the memory map of the registers inside the Legacy Efficiency Monitor and Protocol Checker.

Before reading data in the CSR, you must issue a read command to address 0x01 to take a snapshot of the current data.

Table 354.  Avalon CSR Slave and JTAG Memory Map
Address Bit Name Default Access Description
0x01 31:0 Reserved 0 Read Only Used internally by the EMIF Debug Toolkit to identify Efficiency Monitor type. This address must be read prior to reading the other CSR contents.
0x02 31:0 Reserved Used internally by the EMIF Debug Toolkit to identify Efficiency Monitor version.
0x08 0   Write Only Write a 0 to reset.
7:1 Reserved Reserved for future use.
8   Write Only Write a 0 to reset.
15:9 Reserved Reserved for future use.
16   Read/Write Starting and stopping statistics gathering.
23:17 Reserved Reserved for future use.
31:24 Efficiency Monitor Status Read Only
  • bit 0: Efficiency Monitor stopped
  • bit 1: Waiting for start of pattern
  • bit 2: Running
  • bit 3: Counter saturation
0x10 15:0 Efficiency Monitor address width Read Only Address width of the Efficiency Monitor.
31:16 Efficiency Monitor data width Read Only Data width of the Efficiency Monitor.
0x11 15:0 Efficiency Monitor byte enable Read Only Byte enable width of the Efficiency Monitor.
31:16 Efficiency Monitor burst count width Read Only Burst count width of the Efficiency Monitor.
0x14 31:0 Cycle counter Read Only Clock cycle counter for the Efficiency Monitor. Lists the number of clock cycles elapsed before the Efficiency Monitor stopped.
0x18 31:0 Transfer counter Read Only Counts any read or write data transfer cycle.
0x1C 31:0 Write counter Read Only Counts write requests, including those during bursts.
0x20 31:0 Read counter Read Only Counts read requests.
0x24 31:0 Read total counter Read Only Counts read requests (total burst requests).
0x28 31:0 NTC waitrequest counter Read Only Counts Non Transfer Cycles (NTC) due to slave wait request high.
0x2C 31:0 NTC noreaddatavalid counter Read Only Counts Non Transfer Cycles (NTC) due to slave not having read data.
0x30 31:0 NTC master write idle counter Read Only Counts Non Transfer Cycles (NTC) due to master not issuing command or pause in write burst.
0x34 31:0 NTC master idle counter Read Only Counts Non Transfer Cycles (NTC) due to master not issuing command anytime.
0x40 31:0 Read latency minimum Read Only The lowest read latency value.
0x44 31:0 Read latency maximum Read Only The highest read latency value.
0x48 31:0 Read latency total [31:0] Read Only The lower 32 bits of the total read latency.
0x49 31:0 Read latency total [63:32] Read Only the upper 32 bits of the total read latency.
0x50 7:0 Illegal command Read Only Bits used to indicate which illegal command has occurred. Each bit represents a unique error.
31:8 Reserved Reserved for future use.

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