External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022

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Document Table of Contents mem for QDR II/II+/II+ Xtreme

Interface between FPGA and external memory

Table 96.  Interface: memInterface type: Conduit
Port Name Direction Description
mem_k Output K clock
mem_k_n Output K clock (negative leg)
mem_a Output Address
mem_wps_n Output Write port select
mem_rps_n Output Read port select
mem_doff_n Output DLL turn off
mem_bws_n Output Byte write select
mem_d Output Write data
mem_q Input Read data
mem_cq Input Echo clock
mem_cq_n Input Echo clock (negative leg)

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