External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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6.1.8. Intel Stratix 10 EMIF IP DDR3 Parameters: Diagnostics

Table 197.  Group: Diagnostics / Simulation Options
Display Name Description
Calibration mode Specifies whether to skip memory interface calibration during simulation, or to simulate the full calibration process.

Simulating the full calibration process can take hours (or even days), depending on the width and depth of the memory interface. You can achieve much faster simulation times by skipping the calibration process, but that is only expected to work when the memory model is ideal and the interconnect delays are zero.

If you enable this parameter, the interface still performs some memory initialization before starting normal operations. Abstract PHY is supported with skip calibration.

(Identifier: DIAG_DDR3_SIM_CAL_MODE_ENUM)
Abstract phy for fast simulation Specifies that the system use Abstract PHY for simulation. Abstract PHY replaces the PHY with a model for fast simulation and can reduce simulation time by 3-10 times. Abstract PHY is available for certain protocols and device families, and only when you select Skip Calibration. (Identifier: DIAG_DDR3_ABSTRACT_PHY)
Show verbose simulation debug messages This option allows adjusting the verbosity of the simulation output messages. (Identifier: DIAG_DDR3_SIM_VERBOSE)
Table 198.  Group: Diagnostics / Calibration Debug Options
Display Name Description
Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port Specifies the connectivity of an Avalon slave interface for use by the Quartus Prime EMIF Debug Toolkit or user core logic.

If you set this parameter to "Disabled", no debug features are enabled. If you set this parameter to "Export", an Avalon slave interface named "cal_debug" is exported from the IP. To use this interface with the EMIF Debug Toolkit, you must instantiate and connect an EMIF debug interface IP core to it, or connect it to the cal_debug_out interface of another EMIF core. If you select "Add EMIF Debug Interface", an EMIF debug interface component containing a JTAG Avalon Master is connected to the debug port, allowing the core to be accessed by the EMIF Debug Toolkit.

Only one EMIF debug interface should be instantiated per I/O column. You can chain additional EMIF or PHYLite cores to the first by enabling the "Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export" for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option on all cores after the first.

(Identifier: DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE)
Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port Specifies that the IP export an Avalon-MM master interface (cal_debug_out) which can connect to the cal_debug interface of other EMIF cores residing in the same I/O column. This parameter applies only if the EMIF Debug Toolkit or On-Chip Debug Port is enabled. Refer to the Debugging Multiple EMIFs wiki page for more information about debugging multiple EMIFs. (Identifier: DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER)
First EMIF Instance in the Avalon Chain If selected, this EMIF instance will be the head of the Avalon interface chain connected to the master. For simulation purposes it is needed to identify the first EMIF instance in the avalon Chain. (Identifier: DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN)
Interface ID Identifies interfaces within the I/O column, for use by the EMIF Debug Toolkit and the On-Chip Debug Port. Interface IDs should be unique among EMIF cores within the same I/O column. If the Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port parameter is set to Disabled, the interface ID is unused. (Identifier: DIAG_DDR3_INTERFACE_ID)
Use Soft NIOS Processor for On-Chip Debug Enables a soft Nios processor as a peripheral component to access the On-Chip Debug Port. Only one interface in a column can activate this option. (Identifier: DIAG_SOFT_NIOS_MODE)
Table 199.  Group: Diagnostics / Example Design
Display Name Description
Number of core clocks sharing slaves to instantiate in the example design Specifies the number of core clock sharing slaves to instantiate in the example design. This parameter applies only if you set the "Core clocks sharing" parameter in the "General" tab to "Master" or "Slave". (Identifier: DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES)
Enable In-System-Sources-and-Probes Enables In-System-Sources-and-Probes in the example design for common debug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do driver margining using the EMIF Debug Toolkit. (Identifier: DIAG_DDR3_EX_DESIGN_ISSP_EN)
Table 200.  Group: Diagnostics / Traffic Generator
Display Name Description
Use configurable Avalon traffic generator 2.0 This option allows users to add the new configurable Avalon traffic generator to the example design. (Identifier: DIAG_DDR3_USE_TG_AVL_2)
Bypass the default traffic pattern Specifies that the controller/interface bypass the traffic generator 2.0 default pattern after reset. If you do not enable this parameter, the traffic generator does not assert a pass or fail status until the generator is configured and signaled to start by its Avalon configuration interface. (Identifier: DIAG_DDR3_BYPASS_DEFAULT_PATTERN)
Bypass the user-configured traffic stage Specifies that the controller/interface bypass the user-configured traffic generator's pattern after reset. If you do not enable this parameter, the traffic generator does not assert a pass or fail status until the generator is configured and signaled to start by its Avalon configuration interface.

Configuration can be done by connecting to the traffic generator via the EMIF Debug Toolkit, or by using custom logic connected to the Avalon-MM configuration slave port on the traffic generator. Configuration can also be simulated using the example testbench provided in the altera_emif_avl_tg_2_tb.sv file.

(Identifier: DIAG_DDR3_BYPASS_USER_STAGE)
Bypass the traffic generator repeated-writes/repeated-reads test pattern Specifies that the controller/interface bypass the traffic generator's repeat test stage. If you do not enable this parameter, every write and read is repeated several times. (Identifier: DIAG_DDR3_BYPASS_REPEAT_STAGE)
Bypass the traffic generator stress pattern Specifies that the controller/interface bypass the traffic generator's stress pattern stage. (Stress patterns are meant to create worst-case signal integrity patterns on the data pins.) If you do not enable this parameter, the traffic generator does not assert a pass or fail status until the generator is configured and signaled to start by its Avalon configuration interface. (Identifier: DIAG_DDR3_BYPASS_STRESS_STAGE)
Run diagnostic on infinite test duration Specifies that the traffic generator run indefinitely until the first error is detected. (Identifier: DIAG_DDR3_INFI_TG2_ERR_TEST)
Export Traffic Generator 2.0 configuration interface Specifies that the IP export an Avalon-MM slave port for configuring the Traffic Generator. This is required only if you are configuring the traffic generator through user logic and not through through the EMIF Debug Toolkit. (Identifier: DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE)
Table 201.  Group: Diagnostics / Performance
Display Name Description
Enable Efficiency Monitor Adds an Efficiency Monitor component to the Avalon-MM interface of the memory controller, allowing you to view efficiency statistics of the interface. You can access the efficiency statistics using the EMIF Debug Toolkit. (Identifier: DIAG_DDR3_EFFICIENCY_MONITOR)
Disable P2C Register Stage Disable core register stages for signals entering the core fabric from the periphery. If the core register stages are disabled, latency is reduced but users must ensure that they do not connect the periphery directly to a DSP or a RAM block, without first registering the signals. (Identifier: DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS)
Table 202.  Group: Diagnostics / Miscellaneous
Display Name Description
Use short Qsys interface names Specifies the use of short interface names, for improved usability and consistency with other Qsys components. If this parameter is disabled, the names of Qsys interfaces exposed by the IP will include the type and direction of the interface. Long interface names are supported for backward-compatibility and will be removed in a future release. (Identifier: SHORT_QSYS_INTERFACE_NAMES)
Export PLL lock signal Specifies whether to export the pll_locked signal at the IP top-level to indicate status of PLL. (Identifier: DIAG_EXPORT_PLL_LOCKED)

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