External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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12.2. Bank Management Efficiency

The following figures show examples of how the bank management operations affect controller efficiency.

The first figure shows a read operation in which you have to change a row in a bank. This figure shows how CAS latency and precharge and activate commands affect efficiency.

The following figure illustrates a read-after-write operation. The controller changes the row address after the write-to-read from a different row.

Figure 98. Read Operation—Changing A Row in A Bank


The following sequence of events describes the above figure:

  1. The local_read_req signal goes high, and when the local_ready signal goes high, the controller accepts the read request along with the address.
  2. After the memory receives the last write data, the row changes for read. Now you require a precharge command to close the row opened for write. The controller waits for tWR time (3 memory clock cycles) to give the precharge command after the memory receives the last write data.
  3. After the controller issues the precharge command, it must wait for tRP time to issue an activate command to open a row.
  4. After the controller gives the activate command to activate the row, it needs to wait tRCD time to issue a read command.
  5. After the memory receives the read command, it takes the memory some time to provide the data on the pin. This time is known as CAS latency, which is 3 memory clock cycles in this case.
Note: The tWR, tRP, tRCD, and CAS values depend on memory timing parameters.

For this particular case, you need approximately 17 local clock cycles to issue a read command to the memory. Because the row in the bank changes, the read operation takes a longer time, as the controller has to issue the precharge and activate commands first. You do not have to take into account tWTR for this case because the precharge and activate operations already exceeded tWTR time.

The following figure shows the case where you use the same the row and bank address when the controller switches from write to read. In this case, the read command latency is reduced.

Figure 99. Changing From Write to Read—Same Row and Bank Address


The following sequence of events describes the above figure:

  1. The local_read_req signal goes high and the local_ready signal is high already. The controller accepts the read request along with the address.
  2. When switching from write to read, the controller has to wait tWTR time before it gives a read command to the memory.
  3. The SDRAM device receives the read command.
  4. After the SDRAM device receives the read command, it takes some time to give the data on the pin. This time is called CAS latency, which is 3 memory clock cycles in this case.
Note: The tWTR and CAS values depend on memory timing parameters.

For the case illustrated in the second figure above, you need approximately 11 local clock cycles to issue a read command to the memory. Because the row in the bank remains the same, the controller does not have to issue the precharge and activate commands, which speeds up the read operation and in turn results in a better efficiency compared to the case in the first figure above.

Similarly, if you do not switch between read and write often, the efficiency of your controller improves significantly.

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